Optimal Thermal Management of Microelectronic Packages

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001617-001634
Author(s):  
Victor Chiriac
Keyword(s):  
Thermal Resistance ◽  
Numerical Study ◽  
Metal Layer ◽  
Cost Effective ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach ◽  
System Module ◽  
Multiple Challenges

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, at module and at system (module-board stack-up) levels. The microelectronics industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A 3-D conjugate numerical study was conducted to evaluate the thermal performance of Gallium Arsenic (GaAs) die packaged in Quad Flat No Lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a Power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: 1) one for standard operating parameters and 2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3x3 mm QFN under normal powering conditions is ~138.5°C (or 119°C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ~186°C (or 125°C/W junction-to-air thermal resistance). The top Au metal layer has limited impact on lateral heat spreading. Under extreme powering conditions, the PQFN package reaches a peak temperature of ~126°C (66°C/W thermal resistance). A ~32% reduction in peak temperature is achieved with the 5x5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe and more board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package leads to only 3% reduction in peak temperature. By comparison, the die attach material (conductive epoxy vs. solder) has significant impact on overall reduction in peak temperature (~12%). Experimental measurements using Infrared (IR) Microscope are performed to validate the numerical results.

Thermal Performance Optimization of Radio Frequency Packages for Wireless Communication

2004 ◽  
Vol 126 (4) ◽  
pp. 429-434 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
Vern Hause
Keyword(s):  
Wireless Communication ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Metal Layer ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, either at the module level or at the system (module-board stack-up) level. The wireless communication industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A three-dimensional conjugate numerical study was conducted to evaluate the thermal performance of gallium arsenic die packaged in quad flat no-lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: (1) one for standard operating parameters and (2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3×3 mm QFN under normal powering conditions is ∼138.5 °C (or 119 °C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ∼186 °C (or 125 °C/W junction-to-air thermal resistance). In both cases, the top Au metal layer has a limited impact on lateral heat spreading. Under extreme powering conditions, the 5×5 mm PQFN package reaches a peak temperature of ∼126 °C (66 °C/W thermal resistance). A ∼32% reduction in peak temperature is achieved with the 5×5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe, and additional board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package will lead to only 3% reduction in peak temperature. By comparison, for both packages, the die attach material (conductive epoxy versus solder) will have a significant impact on the overall reduction in peak temperature (∼12%). Experimental measurements using an infrared microscope are performed to validate the numerical results. The results indicate good agreement (∼6% discrepancy) between the numerical model and the measurement.

Thermal Performance Optimization of RF Packages for Wireless Communication

2003 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee ◽  
Vern Hause
Keyword(s):  
Wireless Communication ◽  
Thermal Resistance ◽  
Thermal Performance ◽  
Performance Optimization ◽  
Numerical Study ◽  
Metal Layer ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Board Structure ◽  
Die Attach

The increasing trend in power levels and associated densities leads to the need of design thermal optimization, either at the module level or at the system (module-board stack-up) level. The wireless communication industry is facing multiple challenges as it tries to promote smaller, faster and cost-effective packages, yet trying to cope with potential thermal bottlenecks. The present study investigates a new family of packages, whose thermal and electrical performances are far superior to the classic (standard) packages. A 3-D conjugate numerical study was conducted to evaluate the thermal performance of Gallium Arsenic (GaAs) die packaged in Quad Flat No Lead (QFN) packages for various wireless and networking applications. Two different QFN packages are investigated: a standard package and a Power package (PQFN) with thicker leadframe and solder die attach. The thermal impact of die attach material, leadframe thickness, die pad size, and board structure is evaluated and provides valuable information for product designers. Two powering scenarios are investigated: 1) one for standard operating parameters and 2) an alternative for extreme operating powering scenarios. Results indicate that the peak temperature reached on the die for 3×3 mm QFN under normal powering conditions is ∼138.5°C (or 119°C/W junction-to-air thermal resistance), while for the extreme scenario, the junction temperature is ∼186°C (or 125°C/W junction-to-air thermal resistance). In both cases, the top Au metal layer has a limited impact on lateral heat spreading. Under extreme powering conditions, the 5×5 mm PQFN package reaches a peak temperature of ∼126°C (66°C/W thermal resistance). A ∼32% reduction in peak temperature is achieved with the 5×5 PQFN package. The improvement is mainly due to the larger package size, high conductivity die attach material, thicker leadframe and more board thermal vias. A parametric study shows that the increase in leadframe thickness from 0.2 mm (8 mils) to 0.5 mm (20 mils) in the QFN package will lead to only 3% reduction in peak temperature. By comparison, for both packages, the die attach material (conductive epoxy vs. solder) will have a significant impact on the overall reduction in peak temperature (∼12%). Experimental measurements using an Infrared (IR) Microscope are performed to validate the numerical results. The results indicate good agreement (∼6% discrepancy) between the numerical model and the measurement.

Thermal Performance Evaluation of New Power QFN (Quad Flat No Lead) Packages for Automotive Applications

2004 ◽  
Author(s):  
Victor Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Steady State ◽  
Thermal Performance ◽  
Numerical Study ◽  
Peak Temperature ◽  
Junction Temperature ◽  
Automotive Applications ◽  
Isothermal Boundary ◽  
Die Attach ◽  
Transient Thermal ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the novel Power Quad Flat No Lead (PQFN) packages for automotive applications. Several PQFN packages are investigated, ranging from smaller die/flag size to larger ones, single or multiple heat sources, operating under various powering and boundary conditions. The steady state and transient thermal performance are compared to those of the classical packages, and the impact of the thicker lead frame and die attach material on the overall thermal behavior is also evaluated. Under one steady state (1W) operating scenario, the PQFN package reaches a peak temperature of ~106.3°C, while under 37W@40ms of transient powering, the peak temperature reached by the corner FET is ~260.8°C. With an isothermal boundary (85°C) attached to the board backside, the junction temperature does not change, as the PCB has no significant thermal impact. However, when the isothermal boundary is attached to package bottom, it leads to a drop in by almost 20% after 40 ms. Additional transient cases are evaluated, with an emphasis on the superior thermal performance of this new class of power packages for automotive applications.

System Level Thermal Performance Evaluation of New Inverted Exposed Pad Packages for Automotive Applications

2006 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Peak Temperature ◽  
System Level ◽  
Total Power ◽  
Automotive Applications ◽  
Typical Application ◽  
Cu Alloy ◽  
Die Attach ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the novel 54 lead SOIC (with inverted exposed Cu pad) packages for automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rjhs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, a comparison with a different exposed pad package is made. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package. Several cases are evaluated in the paper, with an emphasis on the superior thermal performance of new packages for automotive applications.

High-Temperature Transient Thermal Analysis for SiC Power Modules

2016 ◽  
Vol 858 ◽  
pp. 1078-1081 ◽  
Author(s):  
Fumiki Kato ◽  
Hiroshi Nakagawa ◽  
Hiroshi Yamaguchi ◽  
Hiroshi Sato
Keyword(s):  
Thermal Analysis ◽  
Heat Capacity ◽  
High Temperature ◽  
Thermal Resistance ◽  
Junction Temperature ◽  
Stable Operation ◽  
Transient Thermal Analysis ◽  
Die Attach ◽  
Power Modules ◽  
Transient Thermal

Transient thermal analysis is a very useful tool for thermal evaluation to realize the stable operation of SiC power modules which are operated at higher temperatures than conventional Si power modules. A transient thermal analysis system to investigate the thermal characteristics of SiC power modules at high temperature is presented. We have found that precise temperature measurement at the initial stage of the junction temperature decay curve is necessary in order to evaluate the thermal resistance and heat capacity of the die attach, since the thermal diffusivity of SiC is larger than that of Si and the temperature distribution of SiC die was considered. Using the proposed transient thermal analysis method, the thermal resistance and heat capacity of the AuGe die attach under the SiC-SBD was successfully evaluated at temperatures up to 250 °C.

Impact of Die Attach Material and Substrate Design on RF GaAs Power Amplifier Devices Thermal Performance

2003 ◽  
Vol 125 (4) ◽  
pp. 589-596 ◽  
Author(s):  
Victor Adrian Chiriac ◽  
Tien-Yu Tom Lee
Keyword(s):  
Thermal Conductivity ◽  
Layer Thickness ◽  
Power Amplifier ◽  
Thermal Performance ◽  
Metal Layer ◽  
Low Cost ◽  
Organic Substrate ◽  
Junction Temperature ◽  
Die Attach ◽  
The Impact

The latest commercial applications for microelectronics use GaAs material for RF power amplifier (PA) devices. This leads to the necessity of identifying low cost packaging solutions with high standards for reliability, electrical, and thermal performance. A detailed thermal analysis for the wirebonded GaAs devices is performed using numerical simulations. The main interest of the study focuses on the impact of die attach thermal conductivity (1.0–50.0 W/mK), substrate’s top metal layer thickness (25–50 μm), and via wall thickness (25–50 μm) on GaAs IC device overall thermal performance. The study uses a two-layer organic substrate. The peak temperatures reached by the PA stages range from 99.6°C to 120.3°C, below the prohibitive/critical value of 150°C (based on 85°C ambient temperature). The increase of die attach thermal conductivity from 1.0 to 7.0 W/mK led to a decrease in peak temperatures of up to 18°C, with larger decay between 1 and 2.4 W/mK. The largest temperature differences were obtained by varying the thermal via thickness, as opposed to only increasing the top metal layer thickness. The peak temperatures and corresponding junction-to-ambient thermal resistances are thoroughly documented. With the same die attach thickness, for a thermal conductivity much larger than 7 W/mK, the impact on the PA’s peak temperature is insignificant. The die attach solder material (with a large thermal conductivity) leads to only a small (2.5°C) decrease in the PA junction temperature.

System Level Thermal Performance Evaluation of Inverted Exposed Pad Packages

2010 ◽  
Vol 2010 (DPC) ◽  
pp. 001635-001655
Author(s):  
Victor Chiriac
Keyword(s):  
Thermal Resistance ◽  
Thermal Performance ◽  
Peak Temperature ◽  
System Level ◽  
Total Power ◽  
Worst Case ◽  
Typical Application ◽  
Cu Alloy ◽  
Die Attach ◽  
The Impact

An extensive 3-D conjugate numerical study is conducted to assess the thermal performance of the 54 lead SOIC (with inverted exposed Cu pad) packages for advanced automotive applications. The thermal performance of the modified designs with exposed pad are investigated, ranging from smaller die/flag size to larger ones, with single or multiple heat sources operating under various powering conditions. The thermal performance is compared to other existing packages with typical application to the automotive industry. The impact of the lead frame geometrical structure and die attach material on the overall thermal behavior is evaluated. Under one steady state (4W) operating scenario, the package reaches a peak temperature of 117.1°C, corresponding to a junction-to-heatsink thermal resistance Rj-hs of 4.27°C/W. For the design with a slightly smaller Cu alloy exposed pad (Cu Alloy), the peak temperature reached by the FETs is 117.8°C, slightly higher than for the design with the intermediate size flag. In this case, the junction-to-heatsink thermal resistance Rj-hs is 4.45°C/W. The worst case powering scenario is identified, with 1.312W/FET and total power of 10.5W, barely satisfying the overall thermal budget. The variation of the peak (junction) temperature is also evaluated for several powering scenarios. Finally, compared different exposed pad packages. The impact of the higher thermal conductivity (solder) die attach is evaluated and compared to the epoxy die attach in the 54 lead SOIC package.

scholarly journals Influence of a Thermal Pad on Selected Parameters of Power LEDs

Energies ◽  
2020 ◽  
Vol 13 (14) ◽  
pp. 3732
Author(s):  
Krzysztof Górecki ◽  
Przemysław Ptak ◽  
Tomasz Torzewicz ◽  
Marcin Janicki
Keyword(s):  
Optical Properties ◽  
Thermal Resistance ◽  
Optical Power ◽  
Junction Temperature ◽  
Operating Parameters ◽  
Cold Plate ◽  
Optical Efficiency ◽  
Forward Current ◽  
Measurement Results ◽  
Set Up

This paper is devoted to the analysis of the influence of thermal pads on electric, optical, and thermal parameters of power LEDs. Measurements of parameters, such as thermal resistance, optical efficiency, and optical power, were performed for selected types of power LEDs operating with a thermal pad and without it at different values of the diode forward current and temperature of the cold plate. First, the measurement set-up used in the paper is described in detail. Then, the measurement results obtained for both considered manners of power LED assembly are compared. Some characteristics that illustrate the influence of forward current and temperature of the cold plate on electric, thermal, and optical properties of the tested devices are presented and discussed. It is shown that the use of the thermal pad makes it possible to achieve more advantageous values of operating parameters of the considered semiconductor devices at lower values of their junction temperature, which guarantees an increase in their lifetime.

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