Reliable Weighted Globally Congestion Aware Routing for Network on Chip

2020 ◽  
Vol 11 (3) ◽  
pp. 48-66
Author(s):  
Habib Chawki Touati ◽  
Fateh Boutekkouk
Keyword(s):  
State Of The Art ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Single Chip ◽  
Transmission Delays ◽  
Data Packets ◽  
Fully Adaptive ◽  
On Chip ◽  
Propagation Network ◽  
Congestion Aware

With the ability to incorporate hundreds of communicating cores on a single chip, thanks to the continuous shrinkage in sizes, communication became of the utmost importance. Consequently, the reduction of transmission delays became unavoidably necessary. All of which is achieved by means of routing algorithms, responsible for selecting the most appropriate routes for data packets, by avoiding congested regions in the network between any pair of source and destination nodes. In this article, two moderately distinct versions in terms of weight distribution of a minimal, fully adaptive, congestion-aware routing scheme in mesh-based network on chip and its accompanying congestion propagation network, are presented. The algorithm does not rely solely on local congestion information nor on irrelevant global information, and provides somewhat a compromise between locally and globally aware routing. The experimental results showcase the proposed scheme's superiority over state of the art NoC routing algorithms.

scholarly journals Congestion-Aware Routing Algorithm for NoC Using Data Packets

2021 ◽  
Vol 2021 ◽  
pp. 1-11
Author(s):  
Khurshid Ahmad ◽  
Muhammad Athar Javed Sethi ◽  
Rehmat Ullah ◽  
Imran Ahmed ◽  
Amjad Ullah ◽  
...  
Keyword(s):  
Routing Algorithm ◽  
Network On Chip ◽  
Routing Algorithms ◽  
System On Chip ◽  
Multiprocessor System ◽  
Data Packets ◽  
Communication Framework ◽  
Using Data ◽  
On Chip ◽  
Congestion Aware

Network on Chip (NoC) is a communication framework for the Multiprocessor System on Chip (MPSoC). It is a router-based communication system. In NoC architecture, nodes of MPSoC are communicating through the network. Different routing algorithms have been developed by researchers, e.g., XY, intermittent XY, DyAD, and DyXY. The main problems in these algorithms are congestion and faults. Congestion and faults cause delay, which degrades the performance of NoC. A congestion-aware algorithm is used for the distribution of traffic over NoC and for the avoidance of congestion. In this paper, a congestion-aware routing algorithm is proposed. The algorithm works by sending congestion information in the data packet. The algorithm is implemented on a 4 × 4 mesh NoC using FPGA. The proposed algorithm decreases latency, increases throughput, and uses less bandwidth in sharing congestion information between routers in comparison to the existing congestion-aware routing algorithms.

YaNoC: Yet Another Network-on-Chip Simulation Acceleration Engine Supporting Congestion-Aware Adaptive Routing Using FPGAs

2019 ◽  
Vol 28 (12) ◽  
pp. 1950202 ◽  
Author(s):  
Khyamling Parane ◽  
B. M. Prabhu Prasad ◽  
Basavaraj Talawar
Keyword(s):  
Design Space Exploration ◽  
Routing Algorithm ◽  
Adaptive Routing ◽  
Network On Chip ◽  
Routing Algorithms ◽  
Tree Topology ◽  
Traffic Pattern ◽  
Mesh Topology ◽  
On Chip ◽  
Congestion Aware

Many-core systems employ the Network on Chip (NoC) as the underlying communication architecture. To achieve an optimized design for an application under consideration, there is a need for fast and flexible NoC simulator. This paper presents an FPGA-based NoC simulation acceleration framework supporting design space exploration of standard and custom NoC topologies considering a full set of microarchitectural parameters. The framework is capable of designing custom routing algorithms, various traffic patterns such as uniform random, transpose, bit complement and random permutation are supported. For conventional NoCs, the standard minimal routing algorithms are supported. For designing the custom topologies, the table-based routing has been implemented. A custom topology called diagonal mesh has been evaluated using table-based and novel shortest path routing algorithm. A congestion-aware adaptive routing has been proposed to route the packets along the minimally congested path. The congestion-aware adaptive routing algorithm has negligible FPGA area overhead compared to the conventional XY routing. Employing the congestion-aware adaptive routing, network latency is reduced by 55% compared to the XY routing algorithm. The microarchitectural parameters such as buffer depth, traffic pattern and flit width have been varied to observe the effect on NoC behavior. For the [Formula: see text] mesh topology, the LUT and FF usages will be increased from 32.23% to 34.45% and from 12.62% to 15% considering the buffer depth of 4 and flit widths of 16 bits, and 32 bits, respectively. Similar behavior has been observed for other configurations of buffer depth and flit width. The torus topology consumes 24% more resources than the mesh topology. The 56-node fat tree topology consumes 27% and 2.2% more FPGA resources than the [Formula: see text] mesh and torus topologies. The 56-node fat tree topology with buffer depth of 8 and 16 flits saturates at the injection rates of 40% and 45%, respectively.

scholarly journals Throughput Enhancement of Continuous Time Replication Strategy using Multicast GALS in NoCs

2020 ◽  
Vol 9 (5) ◽  
pp. 1085-1090
Keyword(s):  
Network On Chip ◽  
System On Chip ◽  
Single Chip ◽  
Data Packets ◽  
Mesh Topology ◽  
Modern Development ◽  
Asynchronous Transmission ◽  
On Chip ◽  
The Impact ◽  
Parallel Communication

The network-on-Chip (NoC) design is the modern development in communication as the integration of the multiple network blocks in a single chip. Before the NoC, system on chip (SoC) was implemented. Development in the day to day the features were added to overcome the SoC like potential of the system on chip, operation frequencies, wiring congestion and size of the chip etc., as the SoC has the long sensitive path which shows the impact on the size of the chip. In wiring congestion: Routing a particular data with SoC requires lot of wirings. Coming to the NoC also developed in packet transferring from source to destination. Serial communication were first used to transfer as it take much time to transfer the data packets from the source to destination to overcome the serial path communication, parallel communication is used. In Parallel communication the packets are transferred from source to destination at a time. To improve the packet transfer in network many techniques are used like mesh topology, tree topology etc. The existing system will supports only the mesh topology and one to many packet transfer. In the proposed system, the new parallel multicast which uses the Globally Asynchronous and locally Synchronous Network on Chip (GALS NoC) that includes both Synchronous and Asynchronous Transmission with a slight change in IPM and OPM Architecture to support both synchronous and asynchronous transmission and reception of data packets. It has several advantages like it supports efficient many-to-one traffic, it is suitable for any topology and has improved Throughput.

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