MSM: Performance Enhancing Area and Congestion Aware Network-on-Chip Architecture

2017 ◽  
Author(s):  
Tuhin Subhra Das ◽  
Prasun Ghosal
Keyword(s):  
Network On Chip ◽  
On Chip ◽  
Congestion Aware ◽  
Performance Enhancing

scholarly journals Congestion-aware wireless network-on-chip for high-speed communication

Automatika ◽  
2019 ◽  
Vol 61 (1) ◽  
pp. 92-98
Author(s):  
M. Devanathan ◽  
V. Ranganathan ◽  
P. Sivakumar
Keyword(s):  
Wireless Network ◽  
High Speed ◽  
Network On Chip ◽  
On Chip ◽  
Congestion Aware

scholarly journals Dual priority congestion aware shared-resource Network-on-Chip architecture

2016 ◽  
Vol 13 (7) ◽  
pp. 20160142-20160142
Author(s):  
Hao Shu ◽  
Jiangyi Shi ◽  
Peijun Ma ◽  
Huaxi Gu ◽  
Weitao Pan ◽  
...  
Keyword(s):  
Network On Chip ◽  
Shared Resource ◽  
Resource Network ◽  
On Chip ◽  
Congestion Aware

scholarly journals BARR: Congestion aware scheduling algorithm for Network-on-Chip router

2017 ◽  
Vol 14 (3) ◽  
pp. 20161247-20161247 ◽  
Author(s):  
Nan Su ◽  
Kun Wang ◽  
Xiaoshan Yu ◽  
Huaxi Gu ◽  
Yantao Guo ◽  
...  
Keyword(s):  
Scheduling Algorithm ◽  
Network On Chip ◽  
On Chip ◽  
Congestion Aware

CAP-W: Congestion-aware platform for wireless-based network-on-chip in many-core era

2017 ◽  
Vol 52 ◽  
pp. 23-33 ◽  
Author(s):  
Amin Rezaei ◽  
Masoud Daneshtalab ◽  
Dan Zhao
Keyword(s):  
Network On Chip ◽  
On Chip ◽  
Many Core ◽  
Congestion Aware

Area and power-efficient innovative congestion-aware Network-on-Chip architecture

2011 ◽  
Vol 57 (1) ◽  
pp. 24-38 ◽  
Author(s):  
Chifeng Wang ◽  
Wen-Hsiang Hu ◽  
Seung Eun Lee ◽  
Nader Bagherzadeh
Keyword(s):  
Network On Chip ◽  
Power Efficient ◽  
On Chip ◽  
Congestion Aware
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