Integration of Optimization Approach Based on Multiple Wordlength Operation Grouping in the AAA Methodology for Real-Time Systems

2014 ◽  
Vol 5 (1) ◽  
pp. 37-60
Author(s):  
Ahmed Ghazi Blaiech ◽  
Khaled Ben Khalifa ◽  
Mohamed Boubaker ◽  
Mohamed Akil ◽  
Mohamed Hedi Bedoui
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Vector Quantization ◽  
Field Programmable Gate Array ◽  
Optimization Approach ◽  
Real Time Systems ◽  
Reconfigurable Circuits ◽  
Field Programmable ◽  
Real Time Applications ◽  
Time Systems

The Multiple-Wordlength Operation Grouping (MWOG) is a recently used approach for an optimized implementation on a Field Programmable Gate Array (FPGA). By fixing the precision constraint, this approach allows minimizing the data wordlength. In this paper, the authors present the integration of the approach based on the MWOG in the Algorithm Architecture Adequation (AAA) methodology, designed to implement real-time applications onto reconfigurable circuits. This new AAA-MWOG methodology will improve the optimization phase of the AAA methodology by taking into account the data wordlength and creating approximative-wordlength operation groups, where the operations in the same group will be performed with the same operator. The AAA-MWOG methodology will allow a considerable gain of circuit resources. This contribution is demonstrated by implementing the Learning Vector Quantization (LVQ) neural-networks model on the FPGA. The LVQ optimization is used to quantify vigilance states starting from processing the electroencephalographic signal. The precision-gain relation has been studied and reported.

Energy Optimization of Mixed-Criticality Distributed Real-Time Embedded Systems

2020 ◽  
pp. 2150085
Author(s):  
Ruoxu Sun ◽  
Jinyu Zhan ◽  
Wei Jiang ◽  
Qi Dong ◽  
Yalan Ye
Keyword(s):  
Real Time ◽  
System Level ◽  
Optimization Approach ◽  
Real Time Systems ◽  
Safety Requirements ◽  
Static Scheduling ◽  
Dynamic Voltage ◽  
Real Time Applications ◽  
Time Systems ◽  
Mixed Criticality

In this paper, we propose a system-level optimization approach for mixed-criticality distributed real-time systems with safety and energy considerations. We firstly depict a mixed-criticality distributed task model for real-time applications, in which the safety of the system is influenced by dynamic voltage and frequency scaling (DVFS). Due to the huge complexity of solving the problem optimally, a heuristic algorithm is proposed to approach the system-level optimization through a quasi-static scheduling strategy. The experiments demonstrate the efficiency of the proposed approach, which can obtain energy consumption while guaranteeing the system safety requirements.

Use of neural networks to recover from software faults in real-time systems

1994 ◽  
Author(s):  
Erwin L. Hunter ◽  
Abhijit S. Pandya ◽  
Neal Coulter
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Real Time Systems ◽  
Software Faults ◽  
Time Systems

scholarly journals A Homogeneous Algorithm for Motion Estimation and Compensation by Using Cellular Neural Networks

2010 ◽  
Vol 5 (5) ◽  
pp. 719 ◽  
Author(s):  
Cristian Grava ◽  
Alexandru Gacsádi ◽  
Ioan Buciu
Keyword(s):  
Neural Networks ◽  
Motion Estimation ◽  
Real Time ◽  
Cellular Neural Networks ◽  
Image Sequences ◽  
Artificial Vision ◽  
Real Time Image ◽  
Field Programmable ◽  
Real Time Applications ◽  
Time Image

In this paper we present an original implementation of a homogeneous algorithm for motion estimation and compensation in image sequences, by using Cellular Neural Networks (CNN). The CNN has been proven their efficiency in real-time image processing, because they can be implemented on a CNN chip or they can be emulated on Field Programmable Gate Array (FPGA). The motion information is obtained by using a CNN implementation of the well-known Horn & Schunck method. This information is further used in a CNN implementation of a motion-compensation method. Through our algorithm we obtain a homogeneous implementation for real-time applications in artificial vision or medical imaging. The algorithm is illustrated on some classical sequences and the results confirm the validity of our algorithm.

Field Programmable Gate Array (FPGA) Based Microwave Oven

2019 ◽  
Vol 892 ◽  
pp. 120-126
Author(s):  
Thangavel Bhuvaneswari ◽  
Nor Hidayati Abdul Aziz ◽  
Jakir Hossen ◽  
Chinthakunta Venkataseshaiah
Keyword(s):  
Real Time ◽  
Field Programmable Gate Array ◽  
Controller Design ◽  
Microwave Oven ◽  
High Potential ◽  
Verilog Hdl ◽  
Quartus Ii ◽  
Field Programmable ◽  
Real Time Applications ◽  
Simulation Results

In this paper, an FPGA-based microwave oven controller design which can be implemented using Altera DE1 development board is presented. The motivation for this work is to explore FPGA for real time applications. First, a microwave oven controller design architecture that could fit into Altera DE1 board, utilizing on-board peripherals is developed. Then, using the proposed architecture, the design is implemented using Verilog HDL. The microwave oven functionalities are demonstrated using Altera DE1 development board by means of Quartus II 13.0 software. The testbenches are created and waveforms are generated using Modelsim 10.1d software. The simulation results for various cases have been presented and the results confirmed that all the basic functionalities of a practical microwave oven can be realized. The proposed FPGA based controller has a high potential for incorporation in microwave ovens.

Timing isolation and improved scheduling of deep neural networks for real‐time systems

2020 ◽  
Vol 50 (9) ◽  
pp. 1760-1777 ◽  
Author(s):  
Daniel Casini ◽  
Alessandro Biondi ◽  
Giorgio Buttazzo
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Deep Neural Networks ◽  
Real Time Systems ◽  
Time Systems

A Real-Time Deep Learning OFDM Receiver

2022 ◽  
Vol 15 (3) ◽  
pp. 1-25
Author(s):  
Stefan Brennsteiner ◽  
Tughrul Arslan ◽  
John Thompson ◽  
Andrew McCormick
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Real Time ◽  
Field Programmable Gate Array ◽  
Orthogonal Frequency Division Multiplexing ◽  
Frequency Division Multiplexing ◽  
Frequency Division ◽  
Field Programmable ◽  
Gate Array ◽  
Fully Connected

Machine learning in the physical layer of communication systems holds the potential to improve performance and simplify design methodology. Many algorithms have been proposed; however, the model complexity is often unfeasible for real-time deployment. The real-time processing capability of these systems has not been proven yet. In this work, we propose a novel, less complex, fully connected neural network to perform channel estimation and signal detection in an orthogonal frequency division multiplexing system. The memory requirement, which is often the bottleneck for fully connected neural networks, is reduced by ≈ 27 times by applying known compression techniques in a three-step training process. Extensive experiments were performed for pruning and quantizing the weights of the neural network detector. Additionally, Huffman encoding was used on the weights to further reduce memory requirements. Based on this approach, we propose the first field-programmable gate array based, real-time capable neural network accelerator, specifically designed to accelerate the orthogonal frequency division multiplexing detector workload. The accelerator is synthesized for a Xilinx RFSoC field-programmable gate array, uses small-batch processing to increase throughput, efficiently supports branching neural networks, and implements superscalar Huffman decoders.

scholarly journals Beyond the Traditional Analyses and Resource Management in Real-Time Systems

2022 ◽  
pp. 67-77
Author(s):  
Federico Reghenzani
Keyword(s):  
Real Time ◽  
Real Time Systems ◽  
Formal Proofs ◽  
Worst Case ◽  
Worst Case Execution Time ◽  
Quantitative Results ◽  
Real Time Applications ◽  
Hard Real Time ◽  
Phd Thesis ◽  
Time Systems

AbstractThe difficulties in estimating the Worst-Case Execution Time (WCET) of applications make the use of modern computing architectures limited in real-time systems. Critical embedded systems require the tasks of hard real-time applications to meet their deadlines, and formal proofs on the validity of this condition are usually required by certification authorities. In the last decade, researchers proposed the use of probabilistic measurement-based methods to estimate the WCET instead of traditional static methods. In this chapter, we summarize recent theoretical and quantitative results on the use of probabilistic approaches to estimate the WCET presented in the PhD thesis of the author, including possible exploitation scenarios, open challenges, and future directions.

VLSI Implementation of Neural Classifiers

1990 ◽  
Vol 2 (1) ◽  
pp. 35-43 ◽  
Author(s):  
Arun Rao ◽  
Mark R. Walker ◽  
Lawrence T. Clark ◽  
L. A. Akers ◽  
R. O. Grondin
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Associative Memory ◽  
Binary Classification ◽  
Real Time Systems ◽  
Classification Schemes ◽  
Pipelined Architecture ◽  
Hardware Implementations ◽  
Fixed Radius ◽  
Time Systems

The embedding of neural networks in real-time systems performing classification and clustering tasks requires that models be implemented in hardware. A flexible, pipelined associative memory capable of operating in real-time is proposed as a hardware substrate for the emulation of neural fixed-radius clustering and binary classification schemes. This paper points out several important considerations in the development of hardware implementations. As a specific example, it is shown how the ART1 paradigm can be functionally emulated by the limited resolution pipelined architecture, in the absence of full parallelism.

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