Timing isolation and improved scheduling of deep neural networks for real‐time systems

2020 ◽  
Vol 50 (9) ◽  
pp. 1760-1777 ◽  
Author(s):  
Daniel Casini ◽  
Alessandro Biondi ◽  
Giorgio Buttazzo
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Deep Neural Networks ◽  
Real Time Systems ◽  
Time Systems

Use of neural networks to recover from software faults in real-time systems

1994 ◽  
Author(s):  
Erwin L. Hunter ◽  
Abhijit S. Pandya ◽  
Neal Coulter
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Real Time Systems ◽  
Software Faults ◽  
Time Systems

VLSI Implementation of Neural Classifiers

1990 ◽  
Vol 2 (1) ◽  
pp. 35-43 ◽  
Author(s):  
Arun Rao ◽  
Mark R. Walker ◽  
Lawrence T. Clark ◽  
L. A. Akers ◽  
R. O. Grondin
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Associative Memory ◽  
Binary Classification ◽  
Real Time Systems ◽  
Classification Schemes ◽  
Pipelined Architecture ◽  
Hardware Implementations ◽  
Fixed Radius ◽  
Time Systems

The embedding of neural networks in real-time systems performing classification and clustering tasks requires that models be implemented in hardware. A flexible, pipelined associative memory capable of operating in real-time is proposed as a hardware substrate for the emulation of neural fixed-radius clustering and binary classification schemes. This paper points out several important considerations in the development of hardware implementations. As a specific example, it is shown how the ART1 paradigm can be functionally emulated by the limited resolution pipelined architecture, in the absence of full parallelism.

scholarly journals Designing Neural Networks for Real-Time Systems

2020 ◽  
pp. 1-1
Author(s):  
Hammond Pearce ◽  
Xin Yang ◽  
Partha S. Roop ◽  
Marc Katzef ◽  
Torur Biskopsto Strom
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Real Time Systems ◽  
Time Systems

Integration of Optimization Approach Based on Multiple Wordlength Operation Grouping in the AAA Methodology for Real-Time Systems

2014 ◽  
Vol 5 (1) ◽  
pp. 37-60
Author(s):  
Ahmed Ghazi Blaiech ◽  
Khaled Ben Khalifa ◽  
Mohamed Boubaker ◽  
Mohamed Akil ◽  
Mohamed Hedi Bedoui
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Vector Quantization ◽  
Field Programmable Gate Array ◽  
Optimization Approach ◽  
Real Time Systems ◽  
Reconfigurable Circuits ◽  
Field Programmable ◽  
Real Time Applications ◽  
Time Systems

The Multiple-Wordlength Operation Grouping (MWOG) is a recently used approach for an optimized implementation on a Field Programmable Gate Array (FPGA). By fixing the precision constraint, this approach allows minimizing the data wordlength. In this paper, the authors present the integration of the approach based on the MWOG in the Algorithm Architecture Adequation (AAA) methodology, designed to implement real-time applications onto reconfigurable circuits. This new AAA-MWOG methodology will improve the optimization phase of the AAA methodology by taking into account the data wordlength and creating approximative-wordlength operation groups, where the operations in the same group will be performed with the same operator. The AAA-MWOG methodology will allow a considerable gain of circuit resources. This contribution is demonstrated by implementing the Learning Vector Quantization (LVQ) neural-networks model on the FPGA. The LVQ optimization is used to quantify vigilance states starting from processing the electroencephalographic signal. The precision-gain relation has been studied and reported.

Fast heuristic scheduling based on neural networks for real-time systems

1995 ◽  
Vol 9 (3) ◽  
pp. 289-304 ◽  
Author(s):  
Ruck Thawonmas ◽  
Goutam Chakraborty ◽  
Norio Shiratori
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
Real Time Systems ◽  
Heuristic Scheduling ◽  
Time Systems

Software Engineering for Real Time Systems

IEE Review ◽  
1992 ◽  
Vol 38 (3) ◽  
pp. 112
Author(s):  
Stuart Bennett
Keyword(s):  
Software Engineering ◽  
Real Time ◽  
Real Time Systems ◽  
Time Systems
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