Nanoscale CuO solid-electrolyte-based conductive-bridging, random-access memory cell with a TiN liner

2018 ◽  
Vol 72 (1) ◽  
pp. 116-121 ◽  
Author(s):  
Jong-Sun Lee ◽  
Dong-Won Kim ◽  
Hea-Jee Kim ◽  
Soo-Min Jin ◽  
Myung-Jin Song ◽  
...  
Keyword(s):  
Solid Electrolyte ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory

Nanoscale CuO solid-electrolyte-based conductive-bridging-random-access-memory cell operating multi-level-cell and 1selector1resistor

2015 ◽  
Vol 3 (37) ◽  
pp. 9540-9550 ◽  
Author(s):  
Kyoung-Cheol Kwon ◽  
Myung-Jin Song ◽  
Ki-Hyun Kwon ◽  
Han-Vit Jeoung ◽  
Dong-Won Kim ◽  
...  
Keyword(s):  
Solid Electrolyte ◽  
Retention Time ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory ◽  
Multi Level

Nanoscale non-volatile CBRAM-cells are developed by using a CuO solid-electrolyte, providing a ∼102memory margin, ∼3 × 106endurance cycles, ∼6.63-years retention time at 85 °C, ∼100 ns writing speed, and MLC operation.

scholarly journals Pre-Emphasis Pulse Design for Random-Access Memory

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa
Keyword(s):  
Time Constant ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Memory Access ◽  
Access Time ◽  
Access Memory ◽  
Delay Times ◽  
Cell Current ◽  
The Impact

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.

Temperature Dependence of Phase-Change Random Access Memory Cell

2006 ◽  
Vol 45 (5A) ◽  
pp. 3955-3958 ◽  
Author(s):  
X. S. Miao ◽  
L. P. Shi ◽  
H. K. Lee ◽  
J. M. Li ◽  
R. Zhao ◽  
...  
Keyword(s):  
Phase Change ◽  
Temperature Dependence ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Access Memory

A Novel Peripheral Circuit for SWSFET Based Multivalued Static Random-Access Memory

2020 ◽  
Vol 29 (01n04) ◽  
pp. 2040010
Author(s):  
R. H. Gudlavalleti ◽  
B. Saman ◽  
R. Mays ◽  
Evan Heller ◽  
J. Chandy ◽  
...  
Keyword(s):  
Quantum Dot ◽  
Quantum Well ◽  
Field Effect Transistors ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Static Random Access Memory ◽  
Access Memory ◽  
Input Gate ◽  
Reduction In Area

This paper presents the peripheral circuitry for a multivalued static random-access memory (SRAM) based on 2-bit CMOS cross-coupled inverters using spatial wavefunction switched (SWS) field effect transistors (SWSFETs). The novel feature is a two quantum well/quantum dot channel n-SWSFET access transistor. The reduction in area with four-bit storage-per-cell increases the memory density and efficiency of the SRAM array. The SWSFET has vertically stacked two-quantum well/quantum dot channels between the source and drain regions. The upper or lower quantum charge locations in the channel region is based on the input gate voltage. The analog behavioral modeling (ABM) of the SWSFET device is done using conventional BSIM 3V3 device parameters in 90 nm technology. The Cadence circuit simulations for the proposed memory cell and addressing/peripheral circuitry are presented.

Analysis of Grain Boundary Dependent Memory Characteristics in Poly-Si One-Transistor Dynamic Random-Access Memory

2021 ◽  
Vol 21 (8) ◽  
pp. 4216-4222
Author(s):  
Songyi Yoo ◽  
In-Man Kang ◽  
Sung-Jae Cho ◽  
Wookyung Sun ◽  
Hyungsoon Shin
Keyword(s):  
Strong Electric Field ◽  
Memory Performance ◽  
Random Access ◽  
Memory Cell ◽  
Random Access Memory ◽  
Dynamic Random Access Memory ◽  
Thin Body ◽  
Memory Cells ◽  
Access Memory ◽  
Memory Characteristics

A capacitorless one-transistor dynamic random-access memory cell with a polysilicon body (poly-Si 1T-DRAM) has a cost-effective fabrication process and allows a three-dimensional stacked architecture that increases the integration density of memory cells. Also, since this device uses grain boundaries (GBs) as a storage region, it can be operated as a memory cell even in a thin body device. GBs are important to the memory characteristics of poly-Si 1T-DRAM because the amount of trapped charge in the GBs determines the memory’s data state. In this paper, we report on a statistical analysis of the memory characteristics of poly-Si 1T-DRAM cells according to the number and location of GBs using TCAD simulation. As the number of GBs increases, the sensing margin and retention time of memory cells deteriorate due to increasing trapped electron charge. Also, “0” state current increases and memory performance degrades in cells where all GBs are adjacent to the source or drain junction side in a strong electric field. These results mean that in poly-Si 1T-DRAM design, the number and location of GBs in a channel should be considered for optimal memory performance.

Sign in / Sign up

Export Citation Format

Share Document