Nanoscale CuO solid-electrolyte-based conductive-bridging-random-access-memory cell operating multi-level-cell and 1selector1resistor

2015 ◽  
Vol 3 (37) ◽  
pp. 9540-9550 ◽  
Author(s):  
Kyoung-Cheol Kwon ◽  
Myung-Jin Song ◽  
Ki-Hyun Kwon ◽  
Han-Vit Jeoung ◽  
Dong-Won Kim ◽  
...  

Nanoscale non-volatile CBRAM-cells are developed by using a CuO solid-electrolyte, providing a ∼102memory margin, ∼3 × 106endurance cycles, ∼6.63-years retention time at 85 °C, ∼100 ns writing speed, and MLC operation.

2018 ◽  
Vol 72 (1) ◽  
pp. 116-121 ◽  
Author(s):  
Jong-Sun Lee ◽  
Dong-Won Kim ◽  
Hea-Jee Kim ◽  
Soo-Min Jin ◽  
Myung-Jin Song ◽  
...  

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1454
Author(s):  
Yoshihiro Sugiura ◽  
Toru Tanzawa

This paper describes how one can reduce the memory access time with pre-emphasis (PE) pulses even in non-volatile random-access memory. Optimum PE pulse widths and resultant minimum word-line (WL) delay times are investigated as a function of column address. The impact of the process variation in the time constant of WL, the cell current, and the resistance of deciding path on optimum PE pulses are discussed. Optimum PE pulse widths and resultant minimum WL delay times are modeled with fitting curves as a function of column address of the accessed memory cell, which provides designers with the ability to set the optimum timing for WL and BL (bit-line) operations, reducing average memory access time.


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