35um CMOS process based Voltage-to-Current Converter Design for Analog OFDM Device

2009 ◽  
Vol 55 (1) ◽  
pp. 336-340 ◽  
Author(s):  
SeongKweon Kim
Keyword(s):  
Cmos Process ◽  
Current Converter ◽  
Converter Design

A High-Transconductance Voltage-to-Current Converter Design

2010 ◽  
Vol 29 (6) ◽  
pp. 1123-1140 ◽  
Author(s):  
M. Mathew ◽  
K. Hayatleh ◽  
B. L. Hart
Keyword(s):  
Current Converter ◽  
Converter Design ◽  
High Transconductance

A HIGH-PRECISION ULTRA-LOW-POWER HYSTERETIC VOLTAGE DETECTOR USING CURRENT-BASED COMPARISON

2013 ◽  
Vol 22 (09) ◽  
pp. 1340005
Author(s):  
WEN-XIAO GU ◽  
MENG-LIAN ZHAO ◽  
XIAO-BO WU ◽  
MINGYANG CHEN ◽  
QING LIU
Keyword(s):  
Low Power ◽  
High Precision ◽  
Total Power ◽  
Cmos Process ◽  
Ultra Low Power ◽  
Total Power Consumption ◽  
Harvesting Systems ◽  
Current Converter ◽  
Average Variation ◽  
A Current

This paper presented a high-precision, ultra-low-power hysteretic voltage detector (HVD) using current comparison to detect voltage default crossing moments for energy-harvesting systems (EHS) in wireless sensor network (WSN) applications. The HVD mainly consists of four parts: a specially designed voltage-to-current converter (VCC) with thermal stability improvement, a comparison core to make current-based comparison, a current pre-amplifier to improve its transient performance and a Schmitt inverter to provide the hysteresis characteristic. The prototype of this HVD has been implemented in SMIC 0.18 μm CMOS process and occupies 0.036 mm2 area without pads. The hysteresis window is about 120 mV wide. The temperature coefficient (TC) is about -170.2 ppm°C. The average variation to different process corners can be reduced to 1.4% by MOSFET and resistor trimming. The total power consumption is only 701.5 nW when VDD is around 1.8 V.

Single-Inductor Dual-Output DC-DC Converter Design Using RC Ripple Regulator Method

2016 ◽  
Vol 136 (2) ◽  
pp. 101-107 ◽  
Author(s):  
Nobukazu Takai ◽  
Shunsuke Tanaka ◽  
Yasunori Kobori ◽  
Haruo Kobayashi
Keyword(s):  
Converter Design

Dual Damascene Process for FatWires in Copper/FSG Technology

2003 ◽  
Vol 766 ◽  
Author(s):  
J. Gambino ◽  
T. Stamper ◽  
H. Trombley ◽  
S. Luce ◽  
F. Allen ◽  
...  
Keyword(s):  
Line Width ◽  
Lower Cost ◽  
Process Window ◽  
Cmos Process ◽  
Dual Damascene ◽  
Damascene Process ◽  
Interconnect Technology

AbstractA trench-first dual damascene process has been developed for fat wires (1.26 μm pitch, 1.1 μm thickness) in a 0.18 μm CMOS process with copper/fluorosilicate glass (FSG) interconnect technology. The process window for the patterning of vias in such deep trenches depends on the trench depth and on the line width of the trench, with the worse case being an intermediate line width (lines that are 3X the via diameter). Compared to a single damascene process, the dual damascene process has comparable yield and reliability, with lower via resistance and lower cost.

A 5-bit 4.2-GS/s Flash ADC in 0.13-µm CMOS Process

2009 ◽  
Vol E92-C (2) ◽  
pp. 258-268 ◽  
Author(s):  
Ying-Zu LIN ◽  
Soon-Jyh CHANG ◽  
Yen-Ting LIU
Keyword(s):  
Cmos Process ◽  
Flash Adc
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