Effects of Shallow Trench Isolation on Silicon-on-Insulator Devices for Mixed Signal Processing

2002 ◽  
Vol 40 (4) ◽  
pp. 653 ◽  
Author(s):  
Lee Hyeokjae ◽  
Park Young June ◽  
Min Hong Shick ◽  
Lee Jong Ho ◽  
Shin Hyungsoon ◽  
...  
Keyword(s):  
Signal Processing ◽  
Silicon On Insulator ◽  
Shallow Trench Isolation ◽  
Mixed Signal ◽  
Trench Isolation

A Novel Retaining Ring in Advanced Polishing Head Design for Significantly Improved CMP Performance

1999 ◽  
Vol 566 ◽  
Author(s):  
Thomas H. Osterheld ◽  
Steve Zuniga ◽  
Sidney Huey ◽  
Peter McKeever ◽  
Chad Garretson ◽  
...  
Keyword(s):  
Device Fabrication ◽  
Silicon On Insulator ◽  
Technological Advancement ◽  
Shallow Trench Isolation ◽  
Trench Isolation ◽  
Retaining Ring

This paper reports a technological advancement in developing and implementing a novel retaining ring of advanced edge performance (AEPTM ring) for an advanced polishing head design. The AEP ring has been successfully used for significantly improved CMP performance in different CMP applications: oxide (PMD and ILD), shallow trench isolation (STI), polysilicon, metal (W and Cu), silicon-on-insulator (SOI), and silicon CMP. Robust processes have been developed using AEP ring along with many hardware upgrades for each application with extended runs to meet requirements of advanced IC device fabrication.

Selective SiGe Etching Formed by Localized Ge Implantation on SOI

2005 ◽  
Vol 108-109 ◽  
pp. 439-444
Author(s):  
Helene Bourdon ◽  
Claire Fenouillet-Béranger ◽  
Claire Gallon ◽  
Philippe Coronel ◽  
Damien Lenoble
Keyword(s):  
Electron Microscopy ◽  
Silicon Germanium ◽  
Secondary Electron ◽  
Silicon On Insulator ◽  
Shallow Trench Isolation ◽  
Fully Depleted ◽  
Atomic Force ◽  
Trench Isolation ◽  
Germanium Layer ◽  
Soi Devices

The fully depleted SOI devices present lateral isolation issues due to the shallow trench isolation (STI) process. We propose in this paper to study a new fabrication process for integrating local isolation trenches. Germanium (Ge) implantation is used to create SiGe (Silicon-Germanium) layer on thin SOI (silicon on insulator) that can be selectively etched. The advantage is the capability of implantation to localize the SiGe area on this substrate and to avoid STI process issues. Aggressive dimensions and geometries are studied and resulting material transformation (crystallization and Ge diffusion) are apprehending via SEM (Secondary Electron Microscopy) or AFM (Atomic Force Spectroscopy) to understand the etching kinetics. After optimization, we demonstrate the capability of fabricating localized trenches on SOI without degrading the neighboring Si layer or consuming the thin BOX (buried oxide).

A New Dummy-Free Shallow Trench Isolation Concept for Mixed-Signal Applications

2000 ◽  
Vol 147 (10) ◽  
pp. 3827 ◽  
Author(s):  
G. Badenes ◽  
R. Rooyackers ◽  
E. Augendre ◽  
E. Vandamme ◽  
C. Perelló ◽  
...  
Keyword(s):  
Shallow Trench Isolation ◽  
Mixed Signal ◽  
Trench Isolation

Micro-Raman Spectroscopy Evaluation of the Local Mechanical Stress in Shallow Trench Isolation CMOS Structures: Correlation with Defect Generation and Diode Leakage

1998 ◽  
Author(s):  
I. De Wolf ◽  
G. Groeseneken ◽  
H.E. Maes ◽  
M. Bolt ◽  
K. Barla ◽  
...  
Keyword(s):  
Raman Spectroscopy ◽  
Mechanical Stress ◽  
Defect Formation ◽  
Active Area ◽  
Wet Oxidation ◽  
Leakage Currents ◽  
Shallow Trench Isolation ◽  
Micro Raman Spectroscopy ◽  
Silicon Devices ◽  
Trench Isolation

Abstract It is shown, using micro-Raman spectroscopy, that Shallow Trench Isolation introduces high stresses in the active area of silicon devices when wet oxidation steps are used. These stresses result in defect formation in the active area, leading to high diode leakage currents. The stress levels are highest near the outer edges of line structures and at square structures. They also increase with decreasing active area dimensions.

Solving the Voltage Contrast on Floating Substrate with Standard FA Toolset

2016 ◽  
Author(s):  
Julien Goxe ◽  
Béatrice Vanhuffel ◽  
Marie Castignolles ◽  
Thomas Zirilli
Keyword(s):  
Electron Microscope ◽  
Scanning Electron Microscope ◽  
Sample Preparation ◽  
Failure Analysis ◽  
Focused Ion Beam ◽  
Ion Beam ◽  
Silicon On Insulator ◽  
Mixed Signal ◽  
Voltage Contrast ◽  
Scanning Electron

Abstract Passive Voltage Contrast (PVC) in a Scanning Electron Microscope (SEM) or a Focused Ion Beam (FIB) is a key Failure Analysis (FA) technique to highlight a leaky gate. The introduction of Silicon On Insulator (SOI) substrate in our recent automotive analog mixed-signal technology highlighted a new challenge: the Bottom Oxide (BOX) layer, by isolating the Silicon Active Area from the bulk made PVC technique less effective in finding leaky MOSFET gates. A solution involving sample preparation performed with standard FA toolset is proposed to enhance PVC on SOI substrate.

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