scholarly journals DESIGN OF A 65 NM CMOS COMPARATOR WITH HYSTERESIS / 65 NM KMOP TECHNOLOGIJOS HISTEREZINIO KOMPARATORIAUS PROJEKTAVIMAS

2014 ◽  
Vol 6 (2) ◽  
pp. 202-205
Author(s):  
Aleksandr Vasjanov ◽  
Vaidotas Barzdėnas
Keyword(s):  
Building Blocks ◽  
Compensation Circuit ◽  
Output Data ◽  
Discrete Device ◽  
Simulation Results ◽  
Offset Compensation ◽  
Zero Voltage ◽  
Hysteresis Parameter

The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator’s circuit. This article presents the results of a CMOS comparator with hysteresis design – the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC. Komparatorius yra vienas iš pagrindinių elektronikos įtaisų. Jis yra naudojamas kaip diskretinis elementas arba kaip viena iš sudėtingesnės sistemos sudedamųjų dalių. Šie įtaisai dažnai veikia elektronikos sistemose, kuriose egzistuoja ne tik informaciją nešantys bei apdorojami signalai, bet ir nepageidautini triukšmo signalai. Siekiant tokiomis sąlygomis užtikrinti patikimą ir efektyvią komparatoriaus veiką, imama taikyti histerezė. Šiame straipsnyje pateikiami TSMC 65 nm KMOP histerezinio komparatoriaus projektavimo rezultatai: aptariama principinė elektrinė schema, pateikiama suprojektuota topologija, jos kompiuterinio modeliavimo rezultatai bei išvados. Šis komparatorius bus naudojamas daugiastandarčio, daugiakanalio siųstuvo-imtuvo grandinėje, nulinio potencialo poslinkio įtampą nustatančiame, lygiagrečios architektūros analoginiame skaitmeniniame keitiklyje (ASK).

Design of 25-Gb/s Half-Rate Clock and Data Recovery Circuit for Optical Communication

2013 ◽  
Vol 385-386 ◽  
pp. 1278-1281 ◽  
Author(s):  
Zheng Fei Hu ◽  
Ying Mei Chen ◽  
Shao Jia Xue
Keyword(s):  
Optical Communication ◽  
Input Data ◽  
Clock And Data Recovery ◽  
Cmos Technology ◽  
Data Recovery ◽  
Phase Detector ◽  
Voltage Controlled Oscillator ◽  
Output Data ◽  
Data Phase ◽  
Simulation Results

A 25-Gb/s clock and data recovery (CDR) circuit with 1:2 demultiplexer which incorporates a quadrature LC voltage-controlled-oscillator and a half-rate bang-bang phase detector is presented in this paper. A quadrature LC VCO is presented to generate the four-phase output clocks. A half-rate phase detector including four flip-flops samples the 25-Gb/s input data every 20 ps and alignes the data phase. The 25-Gb/s data are retimed and demultiplexed into two 12.5-Gb/s output data. The CDR is designed in TSMC 65nm CMOS Technology. Simulation results show that the recovered clock exhibits a peak-to-peak jitter of 0.524ps and the recovered data exhibits a peak-to-peak jitter of 1.2ps. The CDR circuit consumes 121 mW from a 1.2 V supply.

scholarly journals ONLINE PARAMETER IDENTIFICATION OF RICE TRANSPLANTER MODEL BASED ON IPSO-EKF ALGORITHM

2020 ◽  
Vol 61 (2) ◽  
pp. 25-34 ◽  
Author(s):  
Yibo Li ◽  
Hang Li ◽  
Xiaonan Guo
Keyword(s):  
Parameter Identification ◽  
Measured Data ◽  
Model Parameters ◽  
Identification Algorithm ◽  
Output Data ◽  
Swarm Optimization ◽  
Model Based ◽  
Simulation Results ◽  
Filtering Effect ◽  
Ipso Algorithm

In order to improve the accuracy of rice transplanter model parameters, an online parameter identification algorithm for the rice transplanter model based on improved particle swarm optimization (IPSO) algorithm and extended Kalman filter (EKF) algorithm was proposed. The dynamic model of the rice transplanter was established to determine the model parameters of the rice transplanter. Aiming at the problem that the noise matrices in EKF algorithm were difficult to select and affected the best filtering effect, the proposed algorithm used the IPSO algorithm to optimize the noise matrices of the EKF algorithm in offline state. According to the actual vehicle tests, the IPSO-EKF was used to identify the cornering stiffness of the front and rear tires online, and the identified cornering stiffness value was substituted into the model to calculate the output data and was compared with the measured data. The simulation results showed that the accuracy of parameter identification for the rice transplanter model based on the IPSO-EKF algorithm was improved, and established an accurate rice transplanter model.

IBCube

2018 ◽  
Vol 15 (1) ◽  
pp. 27-46
Author(s):  
Qiong Hu ◽  
Hanhua Chen ◽  
Hai Jin ◽  
Chen Tian ◽  
Aobing Sun ◽  
...  
Keyword(s):  
Low Cost ◽  
Packet Delay ◽  
Building Blocks ◽  
Network Interface ◽  
Allocation Scheme ◽  
The Past ◽  
Datacenter Networks ◽  
Construction Scheme ◽  
Economical Design ◽  
Simulation Results

Datacenter networks have attracted a lot of research interest in the past few years. BCube is proved to be a promising scheme due to its low cost. By using a recursive construction scheme, BCube can exponentially scale a datacenter. Industry experiences, however, articulate the importance of incremental expansion of datacenter. In this article, the authors show that BCube's expanding scheme suffers low utilization of switch ports. They propose IBCube, a novel economical design for incrementally building datacenter networks. The insight is that: by letting the number of switches in each BCube layer equal the number of the building blocks, the authors can enable the switch ports to be fully utilized to support the total number of network interface cards of the deployed servers in the datacenters. Accordingly, their IBCube designs a novel automatic port allocation scheme. Simulation results show that the IBCube design reduces the budget for the datacenter networks by 94% as well as improves the packet delay and throughput by 10.3% and 11.5%, respectively, compared to the previous partial BCube design.

Analysis of Full Bridge Series Parallel Resonant Converter for Battery Chargers

2013 ◽  
Vol 768 ◽  
pp. 388-391
Author(s):  
M. Santhosh Rani ◽  
Julie Samantaray ◽  
Subhransu Sekhar Dash
Keyword(s):  
Resonant Frequency ◽  
Resonant Converter ◽  
Battery Charger ◽  
Passive Components ◽  
Turn On ◽  
Secondary Battery ◽  
Battery Chargers ◽  
Zero Current ◽  
Simulation Results ◽  
Zero Voltage

This paper presents a novel application of full-bridge series parallel resonant converter (FBSPRC) for dc source and secondary battery interface. Secondary batteries has been widely used in the application of residential, industrial and commercial energy storage systems because of its low energy conversion loss, which enhances the systems overall efficiency. A series parallel loaded resonant converter (SPRC) which is a subset of DC-DC converter can be operated with either zero-voltage turn-on (above resonant frequency) or zero current turn off (below resonant frequency) to eliminate the turn on and turn-off losses of the semiconductor devices. This converter is widely used to achieve reduction in size of the passive components of the converter such as inductor, capacitor and transformers. Simulation results based on a 12V 45Ah battery charger are proposed to validate the analysis and to demonstrate the performance of the proposed approach. Satisfactory performance is obtained from the measured results. The simulation results validate the effectiveness of the chosen battery charger.

The Nonlinearities of Memoryless Power Amplifier and Model of Predistorter

2014 ◽  
Vol 981 ◽  
pp. 40-45
Author(s):  
Huan Yang ◽  
Yuan Zhi He
Keyword(s):  
Power Amplifier ◽  
Mathematic Model ◽  
Polynomial Model ◽  
Least Square ◽  
Output Data ◽  
Input And Output ◽  
Adaptive Lms ◽  
Simulation Results

By analyzing the input and output data of memoryless power amplifier (PA), we construct the polynomial model and study the nonlinearities characteristics of it. Based on that the mathematic model of predistorter is gained, Least-square (LS) and adaptive LMS are used respectively to solve the question. Simulation results demonstrate predistortion can effectively correct the nonlinearities and both LS and LMS work well depending on different conditions.

Design and Simulation of a New ZVT Bi-directional DC-DC Converter for Electric Vehicles

2017 ◽  
Vol 7 (1) ◽  
pp. 75
Author(s):  
Rajesh Thumma ◽  
Veera Venkata Subrahmanya Kumar Bhajana ◽  
Pramo kumar Aylapogu
Keyword(s):  
Electric Vehicles ◽  
Power Flow ◽  
Low Voltage ◽  
Storage System ◽  
Energy Storage System ◽  
Switching Losses ◽  
Auxiliary Cell ◽  
Bidirectional Converter ◽  
Simulation Results ◽  
Zero Voltage

<p>This paper presents a new zero voltage transistion (ZVT) bi-directional DC-DCconverter for energy storage system in DC traction. This bidirectional converter can transfers the power flow from low voltage side to high voltage side and viceversa. The conventional hard-switched non-isolated converter improved with the additional auxiliary cell to obtain zero voltage transition for the IGBTs. The main advantages of this topology are reduced the switching losses and improved the efficiency as well.The main aim of this converter is to achieve the operation of zero voltage transition during the commutation of main switches from off to on by utilizing auxiliary cell, which consist active and passive elements.The boost and buck modes of operations are achieved with the zero voltage transistion, which reduce the IGBTs current stresses and switching losses.This paper mainly describes the operation principles and the evaluation of the simulation results with the aid of Matlab simulations.The obtained results were proved the expected assumptions of the theoretical analysis.</p>

Chaos in Conditionally Reset Linear Systems

1997 ◽  
Vol 07 (03) ◽  
pp. 177-189
Author(s):  
Cherif Aissi ◽  
Faisal Fadul
Keyword(s):  
Computer Simulation ◽  
Linear Systems ◽  
Building Blocks ◽  
Simple Design ◽  
Nonlinear Controller ◽  
Folding Mechanism ◽  
Simulation Results

This paper presents a novel and simple design of conditionally reset linear systems which exhibit chaotic behevior. The proposed systems are constructed from building blocks e.g. reset integrator, nonlinear controller, summer and gain amplifiers) which can be either designed or found in the off-shelf electronics library. Throughout the paper, computer simulation results are used to show the stretching and folding mechanism for chaos generation in these systems.

Study of Direct Torque Control System of Matrix Converter Multiple Voltage Vectors

2012 ◽  
Vol 588-589 ◽  
pp. 1615-1618
Author(s):  
Zhou Yue
Keyword(s):  
Control System ◽  
Control Strategy ◽  
Direct Torque Control ◽  
Input Voltage ◽  
Torque Ripple ◽  
Matrix Converter ◽  
Torque Control ◽  
Voltage Vector ◽  
Simulation Results ◽  
Zero Voltage

In order to reduce torque ripple. Studied direct torque control of motor that fed by matrix converter. Illustrated control strategy the multiple voltage vector of matrix converter. Full utilize big and small input voltage of matrix converter synthesis long, short and zero voltage vector based on direct torque control of motor that fed by matrix converter, through the rational use of long, short and zero voltage vector to reduce torque ripple. The simulation results demonstrated that the validity of theoretical analysis and modulation strategy presented.

LARGE-SIGNAL ANALYSIS AND SIMULATION OF A ZVT BOOST CONVERTER

2004 ◽  
Vol 13 (03) ◽  
pp. 425-442
Author(s):  
RANGANATHAN GURUNATHAN ◽  
ASHOKA K. S. BHAT
Keyword(s):  
Signal Analysis ◽  
Input Voltage ◽  
Boost Converter ◽  
Soft Switching ◽  
Large Signal ◽  
Spice Simulation ◽  
Simulation Results ◽  
Zero Voltage ◽  
Theoretical Results ◽  
Auxiliary Circuit

Large-signal analysis of a zero-voltage transition (ZVT) boost converter is presented. The proposed ZVT converter uses an auxiliary circuit with two auxiliary switches both having ZVS. Analysis is used to study the converter behavior for step changes in input voltage and load using MATLAB. SPICE simulation results are presented to verify the theoretical results. It is shown that the main switch and auxiliary switches of the proposed converter maintains soft-switching for large-signal transients.

A Circuit for Improving DC-DC Converter Dynamic Response

2013 ◽  
Vol 380-384 ◽  
pp. 3133-3138
Author(s):  
Gui Xi Jia ◽  
He Jiang
Keyword(s):  
Dynamic Response ◽  
Output Voltage ◽  
Output Current ◽  
Voltage Fluctuation ◽  
Compensation Circuit ◽  
Parallel Capacitor ◽  
Wide Range ◽  
Simulation Results

To improve the disadvantage of DC-DC converter output voltage fluctuation when output current changes in wide range, a compensation circuit for improving DC-DC converter dynamic response was presented. The circuit was based on the theory of parallel or anti-parallel capacitor. A charged capacitor was paralleled when output current positive jumped. A charged capacitor was anti-paralleled when output current negative jumped. It worked when output current changed. So DC-DC converter dynamic response was improved and efficiency could be high in the same time. The simulation results proved that the effect of compensation circuit in improving the converter dynamic response and stabilizing the output voltage.

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