scholarly journals Spin Wave Based 4-2 Compressor

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Energy Consumption ◽  
Circuit Design ◽  
Wall Motion ◽  
State Of The Art ◽  
Magnetic Tunnel Junction ◽  
Domain Wall Motion ◽  
The State ◽  
Micromagnetic Simulations ◽  
Low Energy Consumption

By their very nature, Spin Waves (SWs) consume ultra-low amounts of energy, which makes them suitable for ultra-low energy consumption applications. In addition, a compressor can be utilized to further reduce the energy consumption and enhance the speed of a multiplier. Therefore, we propose a novel energy efficient SW based 4-2 compressor consisting of 4 XOR gates and 2 Majority gates. The proposed compressor is validated by means of micromagnetic simulations and compared with the state-of-the-art SW, 22nm CMOS, Magnetic Tunnel Junction (MTJ), Domain Wall Motion (DWM), and Spin-CMOS technologies. The performance evaluation shows that the proposed compressor consumes 2.5x less and 1.25x less energy than the 22nm CMOS and the conventional SW compressor, respectively, whereas it consumes at least 3 orders of magnitude less energy than the MTJ, DWM, and Spin-CMOS designs. Furthermore, the compressor achieves the smallest chip real-estate. In summary, the performance evaluation of our proposed compressor shows that the SW technology has the potential to progress the state-of-the-art circuit design in terms of energy consumption and scalability.

scholarly journals Spin Wave Based 4-2 Compressor

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Performance Evaluation ◽  
Energy Consumption ◽  
Circuit Design ◽  
Wall Motion ◽  
State Of The Art ◽  
Magnetic Tunnel Junction ◽  
Domain Wall Motion ◽  
The State ◽  
Micromagnetic Simulations ◽  
Low Energy Consumption

By their very nature, Spin Waves (SWs) consume ultra-low amounts of energy, which makes them suitable for ultra-low energy consumption applications. In addition, a compressor can be utilized to further reduce the energy consumption and enhance the speed of a multiplier. Therefore, we propose a novel energy efficient SW based 4-2 compressor consisting of 4 XOR gates and 2 Majority gates. The proposed compressor is validated by means of micromagnetic simulations and compared with the state-of-the-art SW, 22nm CMOS, Magnetic Tunnel Junction (MTJ), Domain Wall Motion (DWM), and Spin-CMOS technologies. The performance evaluation shows that the proposed compressor consumes 2.5x less and 1.25x less energy than the 22nm CMOS and the conventional SW compressor, respectively, whereas it consumes at least 3 orders of magnitude less energy than the MTJ, DWM, and Spin-CMOS designs. Furthermore, the compressor achieves the smallest chip real-estate. In summary, the performance evaluation of our proposed compressor shows that the SW technology has the potential to progress the state-of-the-art circuit design in terms of energy consumption and scalability.

scholarly journals Spin Wave Based Full Adder

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Wall Motion ◽  
State Of The Art ◽  
Magnetic Tunnel Junction ◽  
Domain Wall Motion ◽  
Full Adder ◽  
Low Energy ◽  
Phase Detection ◽  
Micromagnetic Simulations ◽  
The Road

Spin Waves (SWs) propagate through magnetic waveguides and interfere with each other without consuming noticeable energy, which opens the road to new ultra-low energy circuit designs. In this paper we build upon SW features and propose a novel energy efficient Full Adder (FA) design consisting of The FA 1 Majority and 2 XOR gates, which outputs Sum and Carry-out are generated by means of threshold and phase detection, respectively. We validate our proposal by means of MuMax3 micromagnetic simulations and we evaluate and compare its performance with state-of-the-art SW, 22nm CMOS, Magnetic Tunnel Junction (MTJ), Spin Hall Effect (SHE), Domain Wall Motion (DWM), and Spin-CMOS implementations. Our evaluation indicates that the proposed SW FA consumes 22.5% and 43% less energy than the direct SW gate based and 22nm CMOS counterparts, respectively. Moreover it exhibits a more than 3 orders of magnitude smaller energy consumption when compared with state-of-the-art MTJ, SHE, DWM, and Spin-CMOS based FAs, and outperforms its contenders in terms of area by requiring at least 22% less chip real-estate.

scholarly journals Spin Wave Based Full Adder

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Sorin Cotofana ◽  
...  
Keyword(s):  
Energy Efficient ◽  
Wall Motion ◽  
State Of The Art ◽  
Magnetic Tunnel Junction ◽  
Domain Wall Motion ◽  
Full Adder ◽  
Low Energy ◽  
Phase Detection ◽  
Micromagnetic Simulations ◽  
The Road

Spin Waves (SWs) propagate through magnetic waveguides and interfere with each other without consuming noticeable energy, which opens the road to new ultra-low energy circuit designs. In this paper we build upon SW features and propose a novel energy efficient Full Adder (FA) design consisting of The FA 1 Majority and 2 XOR gates, which outputs Sum and Carry-out are generated by means of threshold and phase detection, respectively. We validate our proposal by means of MuMax3 micromagnetic simulations and we evaluate and compare its performance with state-of-the-art SW, 22nm CMOS, Magnetic Tunnel Junction (MTJ), Spin Hall Effect (SHE), Domain Wall Motion (DWM), and Spin-CMOS implementations. Our evaluation indicates that the proposed SW FA consumes 22.5% and 43% less energy than the direct SW gate based and 22nm CMOS counterparts, respectively. Moreover it exhibits a more than 3 orders of magnitude smaller energy consumption when compared with state-of-the-art MTJ, SHE, DWM, and Spin-CMOS based FAs, and outperforms its contenders in terms of area by requiring at least 22% less chip real-estate.

scholarly journals Assessing a Multi-Objective Genetic Algorithm with a Simulated Environment for Energy-Saving of Air Conditioning Systems with User Preferences

Symmetry ◽  
2021 ◽  
Vol 13 (2) ◽  
pp. 344
Author(s):  
Alejandro Humberto García Ruiz ◽  
Salvador Ibarra Martínez ◽  
José Antonio Castán Rocha ◽  
Jesús David Terán Villanueva ◽  
Julio Laria Menchaca ◽  
...  
Keyword(s):  
Genetic Algorithm ◽  
Energy Consumption ◽  
Energy Saving ◽  
User Satisfaction ◽  
Air Conditioning ◽  
State Of The Art ◽  
User Preferences ◽  
The State ◽  
Nsga Ii ◽  
Air Conditioning System

Electricity is one of the most important resources for the growth and sustainability of the population. This paper assesses the energy consumption and user satisfaction of a simulated air conditioning system controlled with two different optimization algorithms. The algorithms are a genetic algorithm (GA), implemented from the state of the art, and a non-dominated sorting genetic algorithm II (NSGA II) proposed in this paper; these algorithms control an air conditioning system considering user preferences. It is worth noting that we made several modifications to the objective function’s definition to make it more robust. The energy-saving optimization is essential to reduce CO2 emissions and economic costs; on the other hand, it is desirable for the user to feel comfortable, yet it will entail a higher energy consumption. Thus, we integrate user preferences with energy-saving on a single weighted function and a Pareto bi-objective problem to increase user satisfaction and decrease electrical energy consumption. To assess the experimentation, we constructed a simulator by training a backpropagation neural network with real data from a laboratory’s air conditioning system. According to the results, we conclude that NSGA II provides better results than the state of the art (GA) regarding user preferences and energy-saving.

Non-volatile logic device based on domain-wall motion in a biaxial magnetic tunnel junction

2021 ◽  
Vol 60 (2) ◽  
pp. 020904
Author(s):  
Shuping Li ◽  
Jialin Cai ◽  
Wenxing Lv ◽  
Like Zhang ◽  
Shiheng Liang ◽  
...  
Keyword(s):  
Domain Wall ◽  
Tunnel Junction ◽  
Wall Motion ◽  
Magnetic Tunnel Junction ◽  
Domain Wall Motion ◽  
Logic Device

scholarly journals Spin Wave Based Approximate 4:2 Compressor

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Energy Consumption ◽  
Error Rate ◽  
Energy Efficient ◽  
Directional Coupler ◽  
State Of The Art ◽  
The Other ◽  
Average Error ◽  
Majority Gate ◽  
Micromagnetic Simulations ◽  
Average Error Rate

In this paper, we propose an energy efficient SW based approximate 4:2 compressor comprising a 3-input and a 5-input Majority gate. We validate our proposal by means of micromagnetic simulations, and assess and compare its performance with one of the state-of-the-art SW, 45nm CMOS, and Spin-CMOS counterparts. The evaluation results indicate that the proposed compressor consumes 31.5\% less energy in comparison with its accurate SW design version. Furthermore, it has the same energy consumption and error rate as the approximate compressor with Directional Coupler (DC), but it exhibits 3x lower delay. In addition, it consumes 14% less energy, while having 17% lower average error rate than the approximate 45nm CMOS counterpart. When compared with the other emerging technologies, the proposed compressor outperforms approximate Spin-CMOS based compressor by 3 orders of magnitude in term of energy consumption while providing the same error rate. Finally, the proposed compressor requires the smallest chip real-estate measured in terms of devices.

scholarly journals Voltage Controlled Domain Wall Motion based Neuron and Stochastic Magnetic Tunnel Junction Synapse for Neuromorphic Computing Applications

2021 ◽  
Author(s):  
Aijaz Lone ◽  
Selma Amara ◽  
Hossein Fariborzi
Keyword(s):  
Domain Wall ◽  
Tunnel Junction ◽  
Thermal Noise ◽  
Wall Motion ◽  
Magnetic Tunnel Junction ◽  
Domain Wall Motion ◽  
Spin Orbit ◽  
Free Layer ◽  
Digit Recognition ◽  
Transport Studies

The present work discusses the proposal of a spintronic neuromorphic system with spin orbit torque driven domain wall motion-based neuron and synapse. We propose a voltage-controlled magnetic anisotropy domain wall motion based magnetic tunnel junction neuron. We investigate how the electric field at the gate (pinning site), generated by the voltage signals from pre-neurons, modulates the domain wall motion, which reflects in the non-linear switching behaviour of neuron magnetization. For the implementation of synaptic weights, we propose 3-terminal MTJ with stochastic domain wall motion in the free layer. We incorporate intrinsic pinning effects by creating triangular notches on the sides of the free layer. The pinning of domain wall and intrinsic thermal noise of device lead to the stochastic behaviour of domain wall motion. The control of this stochasticity by the spin orbit torque is shown to realize the potentiation and depression of the synaptic weight. The micromagnetics and spin transport studies in synapse and neuron are carried out by developing a coupled micromagnetic Non-Equilibrium Green’s Function (<i>MuMag-NEGF</i>) model. The minimization of the writing current pulse width by leveraging the thermal noise and demagnetization energy is also presented. Finally, we discuss the implementation of digit recognition by the proposed system using a spike time dependent algorithm.

scholarly journals Spin Wave Based Approximate Computing

2021 ◽  
Author(s):  
Abdulqader Mahmoud ◽  
Frederic Vanderveken ◽  
Florin Ciubotaru ◽  
Christoph Adelmann ◽  
Said Hamdioui ◽  
...  
Keyword(s):  
Real Estate ◽  
Error Rate ◽  
Energy Efficient ◽  
State Of The Art ◽  
Magnetic Tunnel Junction ◽  
Domain Wall Motion ◽  
Full Adder ◽  
Average Error ◽  
Approximate Computing ◽  
Average Error Rate

By their very nature Spin Waves (SWs) enable the realization of energy efficient circuits as they propagate and interfere within waveguides without consuming noticeable energy. However, SW computing can be even more energy efficient by taking advantage of the approximate computing paradigm as many applications are error-tolerant like multimedia and social media. In this paper we propose an ultra-low energy novel Approximate Full Adder (AFA) and a 2-bit inputs Multiplier (AMUL). The approximate FA consists of one Majority gate while the approximate MUL is built by means of 3 AND gates. We validate the correct functionality of our proposal by means of micromagnetic simulations and evaluate the approximate FA figure of merit against state-of-the-art accurate SW, 7nm CMOS, Spin Hall Effect (SHE), Domain Wall Motion (DWM), accurate and approximate 45nm CMOS, Magnetic Tunnel Junction (MTJ), and Spin-CMOS FA implementations. Our results indicate that AFA consumes 43% and 33% less energy than state-of-the-art accurate SW and 7nm CMOS FA, respectively, and saves 69% and 44% when compared with accurate and approximate 45nm CMOS, respectively, and provides a 2 orders of magnitude energy reduction when compared with accurate SHE, accurate and approximate DWM, MTJ, and Spin-CMOS, counterparts. In addition, it achieves the same error rate as approximate 45nm CMOS and Spin-CMOS FA whereas it exhibits 50% less error rate than the approximate DWM FA. Furthermore, it outperforms its contenders in terms of area by saving at least 29% chip real-estate. AMUL is evaluated and compared with state-of-the-art accurate SW and 16nm CMOS accurate and approximate state-of-the-art designs. The evaluation results indicate that it saves at least 2x and 5x energy in comparison with the state-of-the-art SW designs and 16nm CMOS accurate and approximate designs, respectively, and has an average error rate of 10%, while the approximate CMOS MUL has an average error rate of 12.5%, and requires at least 64% less chip real-estate.

TA-MCF: Thermal-Aware Fluid Scheduling for Mixed-Criticality System

2018 ◽  
Vol 28 (02) ◽  
pp. 1950029 ◽  
Author(s):  
Tiantian Li ◽  
Tianyu Zhang ◽  
Ge Yu ◽  
Yichuan Zhang ◽  
Jie Song
Keyword(s):  
Energy Consumption ◽  
State Of The Art ◽  
Schedulability Analysis ◽  
Leakage Power ◽  
The State ◽  
Effect Of Temperature ◽  
Processing Capacity ◽  
Energy Aware ◽  
Fluid Scheduling ◽  
Mixed Criticality

Fluid scheduling allows tasks to be allocated with fractional processing capacity, which significantly improves the schedulability performance. For dual-criticality systems (DCS), dual-rate fluid-based scheduling has been widely studied, e.g., the state-of-the-art approaches mixed-criticality fluid scheduling (MCF) and MC-Sort. However, most of the existing works on DCS either only focus on the schedulability analysis or minimize the energy consumption treating leakage power as a constant. To this end, this paper considers the effect of temperature on leakage power and proposes a thermal and power aware fluid scheduling strategy, referred to as thermal and energy aware (TA)-MCF which minimizes both the energy consumption and temperature, while ensuring a comparable schedulability ratio compared with the MCF and MC-Sort. Extensive experiments validate the efficiency of TA-MCF.

MAGNETIC RACE-TRACK — A NOVEL STORAGE CLASS SPINTRONIC MEMORY

2008 ◽  
Vol 22 (01n02) ◽  
pp. 117-118 ◽  
Author(s):  
STUART PARKIN
Keyword(s):  
Domain Wall ◽  
Tunnel Junction ◽  
Domain Walls ◽  
Magnetic Tunnel Junction ◽  
Domain Wall Motion ◽  
Wall Structure ◽  
Micromagnetic Simulations ◽  
Confining Potential ◽  
Current Pulses ◽  
Race Track

A proposal for a novel storage-class memory is described in which magnetic domains are used to store information in a "magnetic race-track".1 The magnetic race-track shift register storage memory promises a solid state memory with storage capacities and cost rivaling that of magnetic disk drives but with much improved performance and reliability. The magnetic race track is comprised of tall columns of magnetic material arranged perpendicularly to the surface of a silicon wafer. The domains are moved up and down the race-track by nanosecond long current pulses using the phenomenon of spin momentum transfer. The domain walls in the magnetic race-track are read using magnetic tunnel junction magnetoresistive sensing devices arranged in the silicon substrate. Recent progress in developing magnetic tunnel junction devices with giant tunneling magnetoresistance exceeding 350% at room temperature will be mentioned.2 Experiments exploring the current induced motion and depinning of domain walls in magnetic nano-wires with artificial pinning sites will be discussed. The domain wall structure, whether vortex or transverse, and the magnitude of the pinning potential is shown to have surprisingly little effect on the current driven dynamics of the domain wall motion.3 By contrast the motion of DWs under nanosecond long current pulses is surprisingly sensitive to their length.4 In particular, we find that the probability of dislodging a DW, confined to a pinning site in a permalloy nanowire, oscillates with the length of the current pulse, with a period of just a few nanoseconds. Using an analytical model and micromagnetic simulations we show that this behaviour is connected to a current induced oscillatory motion of the DW. The period is determined by the DW mass and the curvature of the confining potential. When the current is turned off during phases of the DW motion when the DW has enough momentum, there is a boomerang effect that can drive the DW out of the confining potential in the opposite direction to the flow of spin angular momentum. Note from Publisher: This article contains the abstract only.

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