scholarly journals Design of a Novel CMOS Voltage Divider

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Power Dissipation ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Voltage Sensing ◽  
Steady Current ◽  
Current Consumption ◽  
Linear Voltage

Passive linear voltage dividers are an essential part of the voltage sensing and detecting circuits. In this paper, a novel voltage divider is designed in 180nm CMOS technology and is validated with LTSpice simulations. The proposed circuit features very low steady current consumption and as a result, very little power dissipation around 200-300pW.

scholarly journals Design of a Novel CMOS Voltage Divider

2021 ◽  
Author(s):  
Darshil Patel
Keyword(s):  
Power Dissipation ◽  
Voltage Divider ◽  
Cmos Technology ◽  
Voltage Sensing ◽  
Steady Current ◽  
Current Consumption ◽  
Linear Voltage

Passive linear voltage dividers are an essential part of the voltage sensing and detecting circuits. In this paper, a novel voltage divider is designed in 180nm CMOS technology and is validated with LTSpice simulations. The proposed circuit features very low steady current consumption and as a result, very little power dissipation around 200-300pW.

Towards the Design of Cost-efficient Generic Register Using Quantum-dot Cellular Automata

2020 ◽  
Vol 10 (4) ◽  
pp. 534-547
Author(s):  
Chiradeep Mukherjee ◽  
Saradindu Panda ◽  
Asish K. Mukhopadhyay ◽  
Bansibadan Maji
Keyword(s):  
Cellular Automata ◽  
Quantum Dot ◽  
Power Dissipation ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Digital Data ◽  
Design Parameters ◽  
Flip Flop ◽  
Quantum Dot Cellular Automata ◽  
Cost Efficient

Background: The advancement of VLSI in the application of emerging nanotechnology explores quantum-dot cellular automata (QCA) which has got wide acceptance owing to its ultra-high operating speed, extremely low power dissipation with a considerable reduction in feature size. The QCA architectures are emerging as a potential alternative to the conventional complementary metal oxide semiconductor (CMOS) technology. Experimental: Since the register unit has a crucial role in digital data transfer between the electronic devices, such study leading to the design of cost-efficient and highly reliable QCA register is expected to be a prudent area of research. A thorough survey on the existing literature shows that the generic models of Serial-in Serial Out (SISO), Serial-in-Parallel-Out (SIPO), Parallel-In- Serial-Out (PISO) and Parallel-in-Parallel-Out (PIPO) registers are inadequate in terms of design parameters like effective area, delay, O-Cost, Costα, etc. Results: This work introduces a layered T gate for the design of the D flip flop (LTD unit), which can be broadly used in SISO, SIPO, PISO, and PIPO register designs. For detection and reporting of high susceptible errors and defects at the nanoscale, the reliability and defect tolerant analysis of LTD unit are also carried out in this work. The QCA design metrics for the general register layouts using LTD unit is modeled. Conclusion: Moreover, the cost metrics for the proposed LTD layouts are thoroughly studied to check the functional complexity, fabrication difficulty and irreversible power dissipation of QCA register layouts.

scholarly journals A Flux Controlled Memristor using 90nm Technology

2021 ◽  
pp. 1-6
Author(s):  
B.T. Krishna ◽  
◽  
Shaik. mohaseena Salma ◽  
Keyword(s):  
Power Supply ◽  
Power Dissipation ◽  
Power Efficiency ◽  
Current Mode ◽  
Cmos Technology ◽  
Theoretical Simulation ◽  
Transconductance Amplifier ◽  
Higher Power ◽  
Static Power ◽  
A Current

A flux-controlled memristor using complementary metal–oxide–(CMOS) structure is presented in this study. The proposed circuit provides higher power efficiency, less static power dissipation, lesser area, and can also reduce the power supply by using CMOS 90nm technology. The circuit is implemented based on the use of a second-generation current conveyor circuit (CCII) and operational transconductance amplifier (OTA) with few passive elements. The proposed circuit uses a current-mode approach which improves the high frequency performance. The reduction of a power supply is a crucial aspect to decrease the power consumption in VLSI. An offered emulator in this proposed circuit is made to operate incremental and decremental configurations well up to 26.3 MHZ in cadence virtuoso platform gpdk using 90nm CMOS technology. proposed memristor circuit has very little static power dissipation when operating with ±1V supply. Transient analysis, memductance analysis, and dc analysis simulations are verified practically with the Experimental demonstration by using ideal memristor made up of ICs AD844AN and CA3080, using multisim which exhibits theoretical simulation are verified and discussed.

scholarly journals Approximate Adder: Lower-Part or Adder

2020 ◽  
Vol 9 (7) ◽  
pp. 1176-1180
Keyword(s):  
Real Time ◽  
Power Dissipation ◽  
High Performance ◽  
Building Blocks ◽  
Cmos Technology ◽  
Approximate Computing ◽  
Computing Technique ◽  
Ripple Carry Adder ◽  
Real Time Applications ◽  
Dsp Systems

High-performance VLSI systems are essential in real-time applications, in order to increase the performance of the VLSI systems, an approximate computing technique is followed where the performance of the circuit is enhanced by trading off it with a slight loss in the accuracy. These approximate circuits are used in error-tolerant applications, where output need not be accurate. This paper concentrates mainly on approximate adders, as they are major building blocks of DSP systems. The analysis of the Lower-part OR Adder for 4-bit addition and comparison of it with the precise adder i.e., Ripple Carry Adder using the mentor graphics tool in 90 nm CMOS technology are presented in this paper. Our experimental results show that there is 17%-70% savings in power dissipation, 4%-32% saving in the area, and 19%-84% savings in time due to approximate adder. As the LOA-2 and LOA-3 are performing optimally these two adders can be used for error-tolerant applications and based on the requirement LOA-2 or LOA-3 can be selected.

scholarly journals Analysis On Power Gating Circuits Based Low Power VLSI Circuits (BCD Adder)

2021 ◽  
Vol 2089 (1) ◽  
pp. 012080
Author(s):  
M. Srinivas ◽  
K.V. Daya Sagar
Keyword(s):  
Energy Consumption ◽  
Low Power ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Oxide Thickness ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Leakage Power ◽  
Vlsi Circuits ◽  
Battery Life

Abstract Currently, energy consumption in the digital circuit is a key design parameter for emerging mobile products. The principal cause of the power dissipation during idle mode is leakage currents, which are rising dramatically. Sub-threshold leakage is increased by the scaling of threshold voltage when gate current leakage increases because oxide thickness is scaled. With rising demands for mobile devices, leakage energy consumption has received even greater attention. Since a mobile device spends most of its time in standby mode, leakage power savings need to prolong the battery life. That is why low power has become a significant factor in CMOS circuit design. The required design and simulation of an AND gate with the BSIM4 MOS parameter model at 27 0C, supply voltage of 0,70V with CMOS technology of 65nm are the validation of the suitability of the proposed circuit technology. AND simulation. The performance parameters for the two AND input gate are compared with the current MTCMOS and SCCMOS techniques, such as sub-threshold leakage power dissipations in active and standby modes, the dynamic dissipation, and propagation period. The proposed hybrid super cutoff complete stack technique compared to the current MTCMOS technology shows a reduction in sub-threshold dissipation power dissipation by 3. 50x and 1.15x in standby modes and active modes respectively. The hybrid surface-cutting technique also shows savings of 2,50 and 1,04 in power dissipation at the sub-threshold in standby modes and active modes compared with the existing SCCMOS Technique.

Thermal-Aware Partitioning and Encoding of Power-Gated FSM

2019 ◽  
Vol 28 (09) ◽  
pp. 1950144
Author(s):  
Priyanka Choudhury ◽  
Kanchan Manna ◽  
Vivek Rai ◽  
Sambhu Nath Pradhan
Keyword(s):  
Power Density ◽  
Power Dissipation ◽  
Hot Spots ◽  
Cmos Technology ◽  
Absolute Temperature ◽  
Temperature Management ◽  
Average Temperature ◽  
Finite State ◽  
Suitable Area ◽  
Power Densities

Miniaturization and the continued scaling of CMOS technology leads to the high-power dissipation and ever-increasing power densities. One of the major challenges for the designer at all design levels is the temperature management, particularly the local hot spots along with power dissipation. In this work, the controller circuits which are implemented as Finite State Machines (FSMs) are considered for their thermal-aware and power-aware realization. Using Genetic Algorithm (GA), both encoding and bipartitioning of the FSM circuit are implemented to get two subFSMs such that at a particular instant of time, one subFSM is active at a time, whereas the other one is power-gated. Again, thermal-aware realization (in terms of power-density) of this power-gated FSM is done. Therefore, the work concerns with the thermal-aware encoding and partitioning of FSM for its power-gated realization. Average temperature saving obtained in this approach for a set of benchmark circuits over previous works is more than 16%. After getting the final partitioned circuit which is optimized in terms of Area and power-density, thermal analysis of the sunFSMs is performed to get the absolute temperature. As thermal-aware design may increase the area, a suitable area-temperature trade-off is also presented in this paper.

A new approach to bypass wire crossing problem in QCA nano technology

Circuit World ◽  
2021 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Ali Majeed ◽  
Esam Alkaldy
Keyword(s):  
Power Dissipation ◽  
Single Layer ◽  
Complementary Metal Oxide Semiconductor ◽  
Full Adder ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Nano Technology ◽  
New Approach ◽  
Content Type ◽  
Wire Crossing

Purpose This study aims to replace current multi-layer and coplanar wire crossing methods in QCA technology to avoid fabrication difficulties caused by them. Design/methodology/approach Quantum-dot cellular automata (QCA) is one of the newly emerging nanoelectronics technology tools that is proposed as a good replacement for complementary metal oxide semiconductor (CMOS) technology. This technology has many challenges, among them being component interconnection and signal routing. This paper will propose a new wire crossing method to enhance layout use in a single layer. The presented method depends on the central cell clock phase to enable two signals to cross over without interference. QCADesigner software is used to simulate a full adder circuit designed with the proposed wire crossing method to be used as a benchmark for further analysis of the presented wire crossing approach. QCAPro software is used for power dissipation analysis of the proposed adder. Findings A new cost function is presented in this paper to draw attention to the fabrication difficulties of the technology when designing QCA circuits. This function is applied to the selected benchmark circuit, and the results show good performance of the proposed method compared to others. The improvement is around 59, 33 and 75% compared to the best reported multi-layer wire crossing, coplanar wire crossing and logical crossing, respectively. The power dissipation analysis shows that the proposed method does not cause any extra power consumption in the circuit. Originality/value In this paper, a new approach is developed to bypass the wire crossing problem in the QCA technique.

scholarly journals Low-Power CMOS Integrated Hall Switch Sensor

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
Rongshan Wei ◽  
Shizhong Guo ◽  
Shanzhi Yang
Keyword(s):  
Supply Voltage ◽  
Reducing Power ◽  
Cmos Technology ◽  
Sleep Mode ◽  
Test Results ◽  
Offset Voltage ◽  
Current Consumption ◽  
Low Power Cmos ◽  
Switch Circuit ◽  
Hall Element

This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit. By optimizing the structure of the Hall element and using the orthogonal coupling and spinning current technology, the offset voltage can be suppressed effectively. The simulation results showed that the Hall switch can eliminate offset voltage greater than 1 mV at 3.3 V supply voltage. Two modes of the Hall switch circuit, the awake mode and the sleep mode, were realized by using clock logic signals without compromising the performance of the Hall switch, thereby reducing power consumption. The test results showed that the operate point and the release point of the switch were within the range of 3–7 mT at 3.3 V supply voltage. Meanwhile, the current consumption is 7.89 µA.

scholarly journals Floating Active Inductor Based Trans-Impedance Amplifier in 0.18 μm CMOS Technology for Optical Applications

Electronics ◽  
2019 ◽  
Vol 8 (12) ◽  
pp. 1547
Author(s):  
Xiangyu Chen ◽  
Yasuhiro Takahashi
Keyword(s):  
Power Dissipation ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Chip Area ◽  
Active Inductors ◽  
Low Pass ◽  
Optical Applications ◽  
Fifth Order

In this paper, a transimpedance amplifier (TIA) based on floating active inductors (FAI) is presented. Compared with conventional TIAs, the proposed TIA has the advantages of a wider bandwidth, lower power dissipation, and smaller chip area. The schematics and characteristics of the FAI circuit are explained. Moreover, the proposed TIA employs the combination of capacitive degeneration, the broadband matching network, and the regulated cascode input stage to enhance the bandwidth and gain. This turns the TIA design into a fifth-order low pass filter with Butterworth response. The TIA is implemented using 0.18 μ m Rohm CMOS technology and consumes only 10.7 mW with a supply voltage of 1.8 V. When used with a 150 fF photodiode capacitance, it exhibits the following characteristics: gain of 41 dB Ω and −3 dB frequency of 10 GHz. This TIA occupies an area of 180 μ m × 118 μ m.

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