scholarly journals Low-Power CMOS Integrated Hall Switch Sensor

2017 ◽  
Vol 2017 ◽  
pp. 1-9 ◽  
Author(s):  
Rongshan Wei ◽  
Shizhong Guo ◽  
Shanzhi Yang
Keyword(s):  
Supply Voltage ◽  
Reducing Power ◽  
Cmos Technology ◽  
Sleep Mode ◽  
Test Results ◽  
Offset Voltage ◽  
Current Consumption ◽  
Low Power Cmos ◽  
Switch Circuit ◽  
Hall Element

This paper presents an integrated Hall switch sensor based on SMIC 0.18 µm CMOS technology. The system includes a front-end Hall element and a back-end signal processing circuit. By optimizing the structure of the Hall element and using the orthogonal coupling and spinning current technology, the offset voltage can be suppressed effectively. The simulation results showed that the Hall switch can eliminate offset voltage greater than 1 mV at 3.3 V supply voltage. Two modes of the Hall switch circuit, the awake mode and the sleep mode, were realized by using clock logic signals without compromising the performance of the Hall switch, thereby reducing power consumption. The test results showed that the operate point and the release point of the switch were within the range of 3–7 mT at 3.3 V supply voltage. Meanwhile, the current consumption is 7.89 µA.

scholarly journals Low-noise and low power CMOS photoreceptor using split-length MOSFET

2019 ◽  
Vol 70 (6) ◽  
pp. 480-485
Author(s):  
Jamel Nebhen ◽  
Julien Dubois ◽  
Sofiene Mansouri ◽  
Dominique Ginhac
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Low Noise ◽  
Vision Sensor ◽  
Current Consumption ◽  
Low Power Cmos ◽  
Design Requirements ◽  
And Performance

Abstract This paper presents the design of a low-power and low-noise CMOS photo-transduction circuit. We propose to use the new technique of composite transistors for noise reduction of photoreceptor in the subthreshold by exploiting the small size effects of CMOS transistors. Several power and noise optimizations, design requirements, and performance limitations relating to the CMOS photoreceptor are presented. This new structure with composite transistors ensures low noise and low power consumption. The CMOS photoreceptor, implemented in a 130 nm standard CMOS technology with a 1.2 V supply voltage, achieves a noise floor of 2μV/⎷Hz within the frequency range from 1 Hz to 10 kHz. The current consumption of the CMOS photoreceptor is 541 nA. This paper shows the need for the design of phototransduction circuit at low voltage, low noise and how these constraints are reflected in the design of CMOS vision sensor.

РАЗРАБОТКА И ИССЛЕДОВАНИЕ СВЕТОДИОДНОГО ДРАЙВЕРА

2020 ◽  
Vol 96 (3s) ◽  
pp. 631-634
Author(s):  
О.Л. Климов ◽  
С.М. Игнатьев ◽  
И.В. Ермаков
Keyword(s):  
Research And Development ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Output Current ◽  
Led Driver ◽  
Voltage Range ◽  
Temperature Range ◽  
Current Consumption ◽  
Current Error

Представлены результаты разработки и исследования светодиодного драйвера в КМОП-технологии уровня 0,6 мкм. Погрешность выходного тока драйвера с учетом технологического разброса в диапазоне напряжений питания от 4 до 20 В и диапазоне температур от -60 до +125 °С составила менее ±5 % от номинального значения 3,55 мА. Ток потребления драйвера - менее 100 мкА, а занимаемая площадь - 0,3 х 0,3 мм2. The paper presents the research and development of the LED driver in 0.6 μm CMOS technology. When the supply voltage range is from 4 to 20 V and temperature range is from -60 to +125 °C the output current error of the LED driver taking into account the process corners is less than ±5 % of the nominal value 3.55 mA. The LED driver current consumption is less than 100 uA and the area is less than 0.3 х 0.3 mm2.

Statistical Simulations on Perceptron-Based Adders

2011 ◽  
pp. 1474-1481
Author(s):  
Snorre Aunet ◽  
Hans Kristian Otnes Berge
Keyword(s):  
Power Consumption ◽  
Supply Voltage ◽  
Reducing Power ◽  
Process Variations ◽  
Full Adder ◽  
Cmos Technology ◽  
Subthreshold Cmos ◽  
Order Of Magnitude ◽  
Supply Voltages ◽  
Circuit Technique

In this article we compare a number of full-adder (1- bit addition) cells regarding minimum supply voltage and yield, when taking statistical simulations into account. According to the ITRS Roadmap two of the most important challenges for future nanoelectronics design are reducing power consumption and increasing manufacturability (ITRS, 2005). We use subthreshold CMOS, which is regarded by many as the most promising ultra low power circuit technique. It is also shown that a minimum redundancyfactor as low as 2 is sufficient to make circuits maintain full functionality under the presence of defects. This is, to our knowledge, the lowest redundancy reported for comparable circuits, and builds on a method suggested a few years ago (Aunet & Hartmann, 2003). A standard Full-Adder (FA) and an FA based on perceptrons exploiting the “mirrored gate”, implemented in a standard 90 nm CMOS technology, are shown not to withstand statistical mismatch and process variations for supply voltages below 150 mV. Exploiting a redundancy scheme tolerating “open” faults, with gate-level redundancy and shorted outputs, shows that the same two FAs might produce adequate Sum and Carry outputs at the presence of a defect PMOS for supply voltages above 150 mV, for a redundancy factor of 2 (Aunet & Otnes Berge, 2007). Two additional perceptrons do not tolerate the process variations, according to simulations. Simulations suggest that the standard FA has the lowest power consumption. Power consumption varies more than an order of magnitude for all subthreshold FAs, due to the statistical variations

ADDRESSING MEMORY EFFECT FOR RAIL-TO-RAIL COMPARATOR WITH NEAR-THRESHOLD SUPPLY VOLTAGE

2013 ◽  
Vol 22 (06) ◽  
pp. 1350048 ◽  
Author(s):  
SARAVANAN RAMAMOORTHY ◽  
HAIBO WANG
Keyword(s):  
Memory Effect ◽  
Threshold Voltage ◽  
Power Supply ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Design Modification ◽  
Offset Voltage ◽  
Rail To Rail ◽  
Near Threshold

Ultra-low voltage comparators with rail-to-rail input ranges are critical components in the design of low-voltage low-power analog to digital converters (ADCs). This paper investigates the memory effect of a commonly used comparator when its power supply is scaled down to near transistor threshold voltage levels. It also studies when such memory effects are most likely to occur during the conversion sequences of successive approximation register (SAR) ADCs. Subsequently an improved comparator design is presented to overcome the memory effect with near-threshold voltage power supply. The impacts of the proposed design modification on comparator speed, offset voltage and power consumptions are discussed. Based on a 0.13 μm CMOS technology and with a 0.5 V power supply, the proposed comparator is compared with the original comparator in terms of memory effect, speed, power consumption and input offset voltage. The integral and differential nonlinearity (INL and DNL) of 10-bit SAR ADCs with using the proposed and original comparators are also compared.

LOGARITHMICAL CURVATURE-CORRECTED VOLTAGE REFERENCES WITH IMPROVED TEMPERATURE BEHAVIOR

2009 ◽  
Vol 18 (03) ◽  
pp. 519-534 ◽  
Author(s):  
COSMIN POPA
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Reference Voltage ◽  
Voltage Reference ◽  
Mos Transistors ◽  
Weak Inversion ◽  
Mos Transistor ◽  
Curvature Correction ◽  
Current Consumption ◽  
Correction Technique

Two voltage reference circuits will be presented. For the first circuit, the linear compensation of V GS (T) for an MOS transistor in subthreshold region will be realized using an original offset voltage follower block as PTAT voltage generator, with the advantages of reducing the silicon area and of increasing accuracy by replacing matched resistors with matched transistors. A new logarithmic curvature-correction technique will be implemented using an asymmetric differential amplifier for compensating the logarithmic temperature dependent term from V GS (T). Because of the operation in weak inversion of all MOS transistors, the circuit will have a very small current consumption, making it compatible with low-power low-voltage designs. The simulated temperature coefficient of the reference voltage for V DD = 2.5 V and a temperature range 0 < t < 30° C is 36.5 ppm/K, confirming the theoretical estimations. The variation of the reference voltage with respect to the supply voltage is 1.5 mV/V for 2–4 V. The circuit current consumption is about 1 μA and the minimal supply voltage is 2 V. The main goal of the second proposed voltage reference is to improve the temperature behavior of a previous reported bipolar voltage reference, by replacing the bipolar transistors with MOS transistors working in weak inversion, with the advantage of obtaining the compatibility with CMOS technology. The new proposed curvature-correction technique will be based on the compensation of the nonlinear temperature dependence of the gate-source voltage for a subthreshold operated MOS transistor by a correction current obtained by taking the difference between two gate-source voltages for MOS transistors biased at drain currents with different temperature dependencies. The circuit is implemented in 0.35 μm CMOS technology. The SPICE simulation confirms the theoretical estimated results, reporting a temperature coefficient of 4.23 ppm/K for the commercial temperature range, 0 < t < 70° C and a small supply voltage, V DD = 2.5 V . The variation of the reference voltage with respect to the supply voltage is 0.9 mV/V for 2–4 V.

The Design of Ultra Low Power RF CMOS LNA in Nanometer Technology

2016 ◽  
pp. 229-251
Author(s):  
Kavyashree P. ◽  
Siva S. Yellampalli
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Noise Figure ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Ultra Low Power ◽  
Low Voltage Operation ◽  
Common Gate ◽  
Low Power Cmos ◽  
Power Application

In this chapter, an ultra low power CMOS Common Gate LNA (CGLNA) with a Capacitive Cross-Coupled (CCC) gm boosting scheme is designed and analysed. The technique described has been employed in literature to reduce the Noise Figure (NF) and power dissipation. In this work we have extended the concept for low voltage operation along with improving NF and also for significant reduction in current consumption. A gm boosted CCC-CGLNA is implemented in 90nm CMOS technology. It has a gain of 9.9dB and a noise figure of 0.87dB at 2.4GHz ISM band and consumes less power (0.5mw) from 0.6V supply voltage. The designed gm boosted CCC-CGLNA is suitable for low power application in CMOS technologies.

scholarly journals Energy Efficient Bandgap Reference Generator for RFID Transponder EEPROM in 130 nm CMOS Process

2019 ◽  
Vol 8 (4) ◽  
pp. 6422-6426
Keyword(s):  
Low Power ◽  
Radio Frequency Identification ◽  
Energy Efficient ◽  
Supply Voltage ◽  
Reducing Power ◽  
Cmos Technology ◽  
Cmos Process ◽  
Bandgap Reference ◽  
Internal Reference ◽  
Power Supply Voltage

Reducing power dissipation of any circuit can make that circuit more energy-efficient and at the same time promise stability. Recent researchers mainly focus on controlling and monitoring low power designs for different low power applications, wireless systems such as radio frequency identification (RFID) transponder. Therefore, generating an internal reference voltage (VR) for the power management unit is the key challenges for researchers to design such applications. Bandgap reference (BGR) is an essential module that assures temperature and independent VR supply in analog circuits. In this research, an improved BGR is designed with the self-startup circuit, bandgap core and an operational amplifier (OP-AMP) to generate a stable VR. A low-power BGR is simulated using Silterra 130 nm CMOS technology. The designed BGR generates a VR of 1.1 V and consumes only 1.4 µA power form 1.2 V power supply voltage. Moreover, it has a temperature coefficient of 41.6 ppm/℃.

An Ultra-Low Power Subthreshold CMOS RSSI for Wake-Up Receiver

2016 ◽  
Vol 25 (08) ◽  
pp. 1650090 ◽  
Author(s):  
Yunzhen Wang ◽  
Shengxi Diao ◽  
Fujiang Lin ◽  
Haiquan Yuan
Keyword(s):  
Low Power ◽  
Dynamic Range ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Subthreshold Region ◽  
Ultra Low Power ◽  
Limiting Amplifier ◽  
Offset Voltage

This paper reports an ultra-low power received signal strength indicator (RSSI) for low frequency (LF) wake-up receiver. Topology theory analysis and subthreshold operation are performed to lower power consumption. Each gain stage of the subthreshold limiting amplifier (LA) employs cascade diode-connected loads to obtain high output impedance while maintaining low power. An offset cancelation circuit with different tail currents, which also operates in the subthreshold region, is employed to reduce the DC offset voltage. Unbalanced source-coupled pairs of subthreshold devices adopted in the full-wave rectification are optimized. A 45[Formula: see text]dB input dynamic range and [Formula: see text][Formula: see text]dB indicating error are achieved at 125[Formula: see text]KHz frequency. The prototype occupies an active area of 0.39[Formula: see text][Formula: see text][Formula: see text]0.28[Formula: see text]mm using CSMC 0.153-[Formula: see text]m complementary metal-oxide-semiconductor (CMOS) technology. With a 1.8[Formula: see text]V supply voltage, the overall current consumption is only 6[Formula: see text][Formula: see text]A.

scholarly journals A Design Methodology Using the Inversion Coefficient for Low-Voltage Low-Power CMOS Voltage References

2011 ◽  
Vol 6 (1) ◽  
pp. 7-17
Author(s):  
Dalton Colombo ◽  
Christian Fayomi ◽  
Frederic Nabki ◽  
Luiz F. Ferreira ◽  
Gilson Wirth ◽  
...  
Keyword(s):  
Low Power ◽  
Design Methodology ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Technology ◽  
Analog Design ◽  
Voltage Reference ◽  
Inversion Coefficient ◽  
Low Power Cmos ◽  
Traditional Approaches

This paper presents an analog design methodology, which uses the selection of the inversion coefficient of MOS devices, to design low-voltage and low-power (LVLP) CMOS voltage references. The motivation of this work comes from the demand for analog design methods that optimize the sizing process of transistors working in subthreshold operation. The advantage of the presented method – compared to the traditional approaches for circuit design – is the reduction of design cycle time and the minimization of simulation iterations when the proposed equations are used. As a case study, a LVLP voltage reference based on subthreshold MOSFETs with a supply voltage of 0.7 V was designed in a 0.18-μm CMOS technology.

scholarly journals An 18.8–33.9 GHz, 2.26 mW Current-Reuse Injection-Locked Frequency Divider for Radar Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (7) ◽  
pp. 2551
Author(s):  
Kwang-Il Oh ◽  
Goo-Han Ko ◽  
Jeong-Geun Kim ◽  
Donghyun Baek
Keyword(s):  
Supply Voltage ◽  
Cmos Technology ◽  
Frequency Divider ◽  
Oxide Semiconductor ◽  
Center Frequency ◽  
Radar Sensor ◽  
Frequency Locking ◽  
Current Reuse ◽  
Sensor Applications ◽  
Locking Range

An 18.8–33.9 GHz, 2.26 mW current-reuse (CR) injection-locked frequency divider (ILFD) for radar sensor applications is presented in this paper. A fourth-order resonator is designed using a transformer with a distributed inductor for wideband operating of the ILFD. The CR core is employed to reduce the power consumption compared to conventional cross-coupled pair ILFDs. The targeted input center frequency is 24 GHz for radar application. The self-oscillated frequency of the proposed CR-ILFD is 14.08 GHz. The input frequency locking range is from 18.8 to 33.8 GHz (57%) at an injection power of 0 dBm without a capacitor bank or varactors. The proposed CR-ILFD consumes 2.26 mW of power from a 1 V supply voltage. The entire die size is 0.75 mm × 0.45 mm. This CR-ILFD is implemented in a 65 nm complementary metal-oxide semiconductor (CMOS) technology.

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