scholarly journals Classification overview of the Hardware Trojans in digital circuits

2020 ◽  
Vol 43 (3) ◽  
pp. 12-15
Author(s):  
Grigore Mihai Timis ◽  
Alexandru Valachi
Keyword(s):  
Integrated Circuit ◽  
Digital Circuits ◽  
Denial Of Service ◽  
Hardware Trojan ◽  
Classification Methods ◽  
Confidential Information ◽  
Hardware Trojans ◽  
Secret Keys

This paper presents an overview of the Hardware Trojans classification methods. A malicious entity can introduce a Hardware Trojan (HT) into a design in order to denial of service, destroy or disable the system. Moreover, it could leak the confidential information and the secret keys before altered them. The Hardware Trojan (HT) threats should be analyzed with maximum importance through the entire lifecycle of the integrated circuit (ICs). A hardware protection against the detected harmful logic should also be implemented.

Implementation Aware Hardware Trojan Trigger

2014 ◽  
Vol 933 ◽  
pp. 482-486
Author(s):  
Masaya Yoshikawa ◽  
Yusuke Mori ◽  
Takeshi Kumaki
Keyword(s):  
Manufacturing Process ◽  
Field Programmable Gate Array ◽  
Large Scale ◽  
Hardware Trojan ◽  
Confidential Information ◽  
Hardware Trojans ◽  
Field Programmable ◽  
Gate Array

Recently, the threat of hardware Trojans has garnered attention. Hardware Trojans are malicious circuits that are incorporated into large-scale integrations (LSIs) during the manufacturing process. When predetermined conditions specified by an attacker are satisfied, the hardware Trojan is triggered and performs subversive activities without the LSI users even being aware of these activities. In previous studies, a hardware Trojan was incorporated into a cryptographic circuit to estimate confidential information. However, Trojan triggers have seldom been studied. The present study develops several new Trojan triggers and each of them is embedded in a field-programmable gate array (FPGA). Subsequently, the ease of detection of each trigger is verified from the standpoint of area.

scholarly journals Creation and Detection of Hardware Trojans Using Non-Invasive Off-The-Shelf Technologies

Electronics ◽  
2018 ◽  
Vol 7 (7) ◽  
pp. 124 ◽  
Author(s):  
Catherine Rooney ◽  
Amar Seeam ◽  
Xavier Bellekens
Keyword(s):  
Integrated Circuits ◽  
Integrated Circuit ◽  
Test Time ◽  
Detection Accuracy ◽  
Sensitive Information ◽  
Hardware Trojan ◽  
Hardware Trojans ◽  
Non Invasive ◽  
Channel Analysis ◽  
Open Source Hardware

As a result of the globalisation of the semiconductor design and fabrication processes, integrated circuits are becoming increasingly vulnerable to malicious attacks. The most concerning threats are hardware trojans. A hardware trojan is a malicious inclusion or alteration to the existing design of an integrated circuit, with the possible effects ranging from leakage of sensitive information to the complete destruction of the integrated circuit itself. While the majority of existing detection schemes focus on test-time, they all require expensive methodologies to detect hardware trojans. Off-the-shelf approaches have often been overlooked due to limited hardware resources and detection accuracy. With the advances in technologies and the democratisation of open-source hardware, however, these tools enable the detection of hardware trojans at reduced costs during or after production. In this manuscript, a hardware trojan is created and emulated on a consumer FPGA board. The experiments to detect the trojan in a dormant and active state are made using off-the-shelf technologies taking advantage of different techniques such as Power Analysis Reports, Side Channel Analysis and Thermal Measurements. Furthermore, multiple attempts to detect the trojan are demonstrated and benchmarked. Our simulations result in a state-of-the-art methodology to accurately detect the trojan in both dormant and active states using off-the-shelf hardware.

Hardware Trojan Detection Technique Using Frequency Characteristic Analysis of Path Delay in Application Specific Integrated Circuits

2020 ◽  
Vol 10 (2) ◽  
pp. 36-43
Author(s):  
Ha Thai Tran ◽  
Phuc Van Hoang ◽  
Tuan Ngoc Do ◽  
Duong Hai Nguyen
Keyword(s):  
Integrated Circuits ◽  
Frequency Characteristic ◽  
Integrated Circuit ◽  
Hardware Security ◽  
Hardware Trojan ◽  
Path Delay ◽  
Characteristic Analysis ◽  
Hardware Trojan Detection ◽  
Ic Manufacturing ◽  
Application Specific

 Abstract—  Since the last decade, hardware Trojan (HT) have become a serious problem for hardware security because of outsourcing trends in Integrated Circuit (IC) manufacturing. As the fabrication of IC is becoming very complex and costly, more and more chipmakers outsource their designs or parts of the fabrication process. This trend opens a loophole in hardware security, as an untrusted company could perform malicious modifications to the golden circuit at design or fabrication stages. Therefore, assessing risks and proposing solutions to detect HT are very important tasks. This paper presents a technique for detecting HT using frequency characteristic analysis of path delay. The results show that measuring with the frequency step of 0.016 MHz can detect a HT having the size of 0.2% of the original design.Tóm tắt— Từ thập niên 2010, Trojan phần cứng (HT) đã trở thành một vấn đề nghiêm trọng đối với bảo mật phần cứng, do xu hướng thuê sản xuất mạch tích hợp (Integrated Circuit - IC). Khi quá trình chế tạo IC trở nên phức tạp và tốn kém, ngày càng nhiều nhà sản xuất chip lựa chọn phương án thuê lại một phần hoặc toàn bộ thiết kế IC. Xu hướng này tạo ra lỗ hổng trong bảo mật phần cứng, vì một công ty không đáng tin cậy có thể thực hiện các sửa đổi độc hại vào trong mạch nguyên bản ở giai đoạn thiết kế hoặc chế tạo. Do đó, đánh giá rủi ro và đề xuất giải pháp phát hiện HT là một trong những nhiệm vụ hết sức quan trọng. Bài báo này trình bày một giải pháp phát hiện HT sử dụng phân tích đặc tính tần số của độ trễ đường truyền tín hiệu. Kết quả cho thấy, thực hiện khảo sát với bước tần số 0,016 MHz có thể phát hiện được HT có kích thước 0,2% so với thiết kế ban đầu. 

scholarly journals Think Smart, Play Dumb: Analyzing Deception in Hardware Trojan Detection Using Game Theory

2020 ◽  
Author(s):  
Tapadhir Das
Keyword(s):  
Integrated Circuits ◽  
Repeated Game ◽  
Third Party ◽  
Hardware Trojan ◽  
Hardware Trojans ◽  
Learning Stage ◽  
Hardware Trojan Detection ◽  
Trojan Detection ◽  
Utility Gain ◽  
Game Theoretic

In recent years, integrated circuits (ICs) have become<br>significant for various industries and their security has<br>been given greater priority, specifically in the supply chain.<br>Budgetary constraints have compelled IC designers to offshore manufacturing to third-party companies. When the designer gets the manufactured ICs back, it is imperative to test for potential threats like hardware trojans (HT). In this paper, a novel multilevel game-theoretic framework is introduced to analyze the interactions between a malicious IC manufacturer and the tester. In particular, the game is formulated as a non-cooperative, zerosum, repeated game using prospect theory (PT) that captures different players’ rationalities under uncertainty. The repeated game is separated into a learning stage, in which the defender<br><div>learns about the attacker’s tendencies, and an actual game stage, where this learning is used. Experiments show great incentive for the attacker to deceive the defender about their actual rationality by “playing dumb” in the learning stage (deception). This scenario is captured using hypergame theory to model the attacker’s view of the game. The optimal deception rationality of the attacker is analytically derived to maximize utility gain. For the defender, a first-step deception mitigation process is proposed to thwart the effects of deception. Simulation results show that the attacker can profit from the deception as it can successfully insert HTs in the manufactured ICs without being detected.</div><div><br></div><div>This paper has been accepted for publication in <b>IEEE Cyber Science Conference 2020</b><br></div>

A Statistical Test Generation Based on Mutation Analysis for Improving the Hardware Trojan Detection

2019 ◽  
Vol 29 (03) ◽  
pp. 2050049
Author(s):  
Yanjiang Liu ◽  
Yiqiang Zhao ◽  
Jiaji He ◽  
Ruishan Xin
Keyword(s):  
Mutation Analysis ◽  
Integrated Circuit ◽  
Test Generation ◽  
Process Variations ◽  
Statistical Test ◽  
Detection Sensitivity ◽  
Hardware Trojan ◽  
Trojan Detection ◽  
Test Vectors ◽  
Low Activity

Hardware Trojan has become a major threat to the security and trustworthiness of integrated circuit (IC) employed in critical applications. Due to the presence of process variations and measurement noises, all existing side-channel Trojan detection approaches suffer from low detection sensitivity or even false negatives with increasing circuit size and decreasing Trojan size. In this paper, we propose a statistical test generation approach based on mutation analysis, which generates a set of test vectors aiming at activating the hardware Trojan inserted into the low activity nodes. Such approach not only enhances the controllability of low activity nodes through increasing the switching activity of it, but also improves the observability by propagating the artificial designed errors introduced by the mutant to the outputs. Simulation results of a set of ISCAS’85 and ISCAS’89 benchmark circuits show that the proposed approach improves the activity of low activity nodes 463% at most compared with the Multiple Excitation of Rare Occurrence (MERO) approach and increases the Trojan coverage with 84.08% reduction in test length. Moreover, the test vectors generated by the proposed approach and the MERO approach, respectively, are exerted to the circuit under test. Experimental results demonstrate that the Mahalanobis distance margin of the proposed approach is much greater than the MERO approach, and thus provide a comparable robustness with decreasing Trojan size.

Implementing hardware Trojans: Experiences from a hardware Trojan challenge

2011 ◽  
Author(s):  
Georg T. Becker ◽  
Ashwin Lakshminarasimhan ◽  
Lang Lin ◽  
Sudheendra Srivathsa ◽  
Vikram B. Suresh ◽  
...  
Keyword(s):  
Hardware Trojan ◽  
Hardware Trojans

scholarly journals Attack Mitigation of Hardware Trojans for Thermal Sensing via Micro-ring Resonator in Optical NoCs

2021 ◽  
Vol 17 (3) ◽  
pp. 1-23
Author(s):  
Jun Zhou ◽  
Mengquan Li ◽  
Pengxing Guo ◽  
Weichen Liu
Keyword(s):  
Optical Networks ◽  
Ring Resonator ◽  
Denial Of Service ◽  
Third Party ◽  
Temperature Sensitive ◽  
Hardware Trojans ◽  
Detection Scheme ◽  
Attack Model ◽  
Thermal Sensing ◽  
On Chip

As an emerging role in new-generation on-chip communication, optical networks-on-chip (ONoCs) provide ultra-high bandwidth, low latency, and low power dissipation for data transfers. However, the thermo-optic effects of the photonic devices have a great impact on the operating performance and reliability of ONoCs, where the thermal-aware control with accurate measurements, e.g., thermal sensing, is typically applied to alleviate it. Besides, the temperature-sensitive ONoCs are prone to be attacked by the hardware Trojans (HTs) covertly embedded in the counterfeit integrated circuits (ICs) from the malicious third-party vendors, leading to performance degradation, denial-of-service (DoS), or even permanent damages. In this article, we focus on the tampering and snooping attacks during the thermal sensing via micro-ring resonator (MR) in ONoCs. Based on the provided workflow and attack model, a new structure of the anti-HT module is proposed to verify and protect the obtained data from the thermal sensor for attacks in its optical sampling and electronic transmission processes. In addition, we present the detection scheme based on the spiking neural networks (SNNs) to implement an accurate classification of the network security statuses for further high-level control. Evaluation results indicate that, with less than 1% extra area of a tile, our approach can significantly enhance the hardware security of thermal sensing for ONoC with trivial costs of up to 8.73%, 5.32%, and 6.14% in average latency, execution time, and energy consumption, respectively.

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