Adhesives for floor covering. Requirements for mechanical and electrical performance

2003 ◽  
Keyword(s):  
Electrical Performance ◽  
Floor Covering

Metal Microstructures in Advanced CMOS Devices

1996 ◽  
Vol 54 ◽  
pp. 358-359
Author(s):  
L. M. Gignac ◽  
K. P. Rodbell
Keyword(s):  
Grain Boundaries ◽  
Semiconductor Device ◽  
Chemical Vapor ◽  
Microstructural Characterization ◽  
Metal Films ◽  
Thin Metal ◽  
Electrical Performance ◽  
Thin Metal Films ◽  
Chemical Vapor Deposited ◽  
Boundary Properties

As advanced semiconductor device features shrink, grain boundaries and interfaces become increasingly more important to the properties of thin metal films. With film thicknesses decreasing to the range of 10 nm and the corresponding features also decreasing to sub-micrometer sizes, interface and grain boundary properties become dominant. In this regime the details of the surfaces and grain boundaries dictate the interactions between film layers and the subsequent electrical properties. Therefore it is necessary to accurately characterize these materials on the proper length scale in order to first understand and then to improve the device effectiveness. In this talk we will examine the importance of microstructural characterization of thin metal films used in semiconductor devices and show how microstructure can influence the electrical performance. Specifically, we will review Co and Ti silicides for silicon contact and gate conductor applications, Ti/TiN liner films used for adhesion and diffusion barriers in chemical vapor deposited (CVD) tungsten vertical wiring (vias) and Ti/AlCu/Ti-TiN films used as planar interconnect metal lines.

Effective performance improvement of organic thin film transistors with multi-layer modifications

2020 ◽  
Vol 91 (3) ◽  
pp. 30201
Author(s):  
Hang Yu ◽  
Jianlin Zhou ◽  
Yuanyuan Hao ◽  
Yao Ni
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Performance Enhancement ◽  
Organic Thin Film Transistors ◽  
Electrical Performance ◽  
Hole Injection ◽  
Organic Thin Film ◽  
Effective Performance ◽  
Significant Performance ◽  
P Type

Organic thin film transistors (OTFTs) based on dioctylbenzothienobenzothiophene (C8BTBT) and copper (Cu) electrodes were fabricated. For improving the electrical performance of the original devices, the different modifications were attempted to insert in three different positions including semiconductor/electrode interface, semiconductor bulk inside and semiconductor/insulator interface. In detail, 4,4′,4′′-tris[3-methylpheny(phenyl)amino] triphenylamine (m-MTDATA) was applied between C8BTBTand Cu electrodes as hole injection layer (HIL). Moreover, the fluorinated copper phthalo-cyanine (F16CuPc) was inserted in C8BTBT/SiO2 interface to form F16CuPc/C8BTBT heterojunction or C8BTBT bulk to form C8BTBT/F16CuPc/C8BTBT sandwich configuration. Our experiment shows that, the sandwich structured OTFTs have a significant performance enhancement when appropriate thickness modification is chosen, comparing with original C8BTBT devices. Then, even the low work function metal Cu was applied, a normal p-type operate-mode C8BTBT-OTFT with mobility as high as 2.56 cm2/Vs has been fabricated.

Degradation and SILC Effects of RPECVD sub-2.0nm Oxide/Nitride and Oxynitride Dielectrics Under Constant Current Stress

2002 ◽  
Vol 716 ◽  
Author(s):  
Yi-Mu Lee ◽  
Yider Wu ◽  
Joon Goo Hong ◽  
Gerald Lucovsky
Keyword(s):  
Leakage Current ◽  
Electrical Performance ◽  
Constant Current ◽  
Continuous Increase ◽  
Current Stress ◽  
Thermal Oxide ◽  
Stress Induced Leakage Current ◽  
Boron Penetration ◽  
Soft Breakdown ◽  
Induced Defects

AbstractConstant current stress (CCS) has been used to investigate the Stress-Induced Leakage Current (SILC) to clarify the influence of boron penetration and nitrogen incorporation on the breakdown of p-channel devices with sub-2.0 nm Oxide/Nitride (O/N) and oxynitride dielectrics prepared by remote plasma enhanced CVD (RPECVD). Degradation of MOSFET characteristics correlated with soft breakdown (SBD) and hard breakdown (HBD), and attributed to the increased gate leakage current are studied. Gate voltages were gradually decreased during SBD, and a continuous increase in SILC at low gate voltages between each stress interval, is shown to be due to the generation of positive traps which are enhanced by boron penetration. Compared to thermal oxides, stacked O/N and oxynitride dielectrics with interface nitridation show reduced SILC due to the suppression of boron penetration and associated positive trap generation. Devices stressed under substrate injection show harder breakdown and more severe degradation, implying a greater amount of the stress-induced defects at SiO2/substrate interface. Stacked O/N and oxynitride devices also show less degradation in electrical performance compared to thermal oxide devices due to an improved Si/SiO2 interface, and reduced gate-to-drain overlap region.

Correlation Between the Tunnelling Oxide and I-V Curves of MIS Photodiodes

2003 ◽  
Vol 762 ◽  
Author(s):  
H. Águas ◽  
L. Pereira ◽  
A. Goullet ◽  
R. Silva ◽  
E. Fortunato ◽  
...  
Keyword(s):  
Hydrogen Peroxide ◽  
Oxide Layer ◽  
Spectroscopic Ellipsometry ◽  
Chemical Deposition ◽  
Oxide Thickness ◽  
Electrical Performance ◽  
Signal To Noise ◽  
Rectification Factor ◽  
Mis Devices ◽  
The Ideal

AbstractIn this work we present results of a study performed on MIS diodes with the following structure: substrate (glass) / Cr (2000Å) / a-Si:H n+ (400Å) / a-Si:H i (5500Å) / oxide (0-40Å) / Au (100Å) to determine the influence of the oxide passivation layer grown by different techniques on the electrical performance of MIS devices. The results achieved show that the diodes with oxides grown using hydrogen peroxide present higher rectification factor (2×106)and signal to noise (S/N) ratio (1×107 at -1V) than the diodes with oxides obtained by the evaporation of SiO2, or by the chemical deposition of SiO2 by plasma of HMDSO (hexamethyldisiloxane), but in the case of deposited oxides, the breakdown voltage is higher, 30V instead of 3-10 V for grown oxides. The ideal oxide thickness, determined by spectroscopic ellipsometry, is dependent on the method used to grow the oxide layer and is in the range between 6 and 20 Å. The reason for this variation is related to the degree of compactation of the oxide produced, which is not relevant for applications of the diodes in the range of ± 1V, but is relevant when high breakdown voltages are required.

Effect of Illumination on Organic Polymer Thin-Film Transistors

2003 ◽  
Vol 771 ◽  
Author(s):  
Michael C. Hamilton ◽  
Sandrine Martin ◽  
Jerzy Kanicki
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Drain Current ◽  
Charge Carriers ◽  
Electrical Performance ◽  
Organic Polymer ◽  
Light Illumination ◽  
Polymer Thin Film ◽  
Channel Region ◽  
White Light Illumination

AbstractWe have investigated the effects of white-light illumination on the electrical performance of organic polymer thin-film transistors (OP-TFTs). The OFF-state drain current is significantly increased, while the drain current in the strong accumulation regime is relatively unaffected. At the same time, the threshold voltage is decreased and the subthreshold slope is increased, while the field-effect mobility of the charge carriers is not affected. The observed effects are explained in terms of the photogeneration of free charge carriers in the channel region due to the absorbed photons.

A novel process for SiGe Core-Shell JAM Transistors Fabrication and thermal annealing effect on its electrical performance

2020 ◽  
Vol 1 (2) ◽  
Author(s):  
Ashish Kumar ◽  
Wen-Hsi Lee
Keyword(s):  
Process Condition ◽  
Subthreshold Swing ◽  
Electrical Performance ◽  
Core Shell ◽  
Electrical Characteristics ◽  
Thermal Budget ◽  
New Process ◽  
Comparable Performance ◽  
Higher Temperature ◽  
Film Annealing

 In this study, we fabricate Si/SiGe core-shell Junctionless accumulation mode (JAM)FinFET devices through a rapid and novel process with four main steps, i.e. e-beam lithography definition, sputter deposition, alloy combination annealing, and chemical solution etching. The height of Si core is 30 nm and the thickness of Si/SiGe core-shell is about 2 nm. After finishing the fabrication of devices, we widely studied the electrical characteristics of poly Si/SiGe core-shell JAM FinFET transistors from a view of different Lg and Wch. A poly-Si/SiGe core -shell JAMFETs was successfully demonstrated and it also exhibits  a superior subthreshold swing of 81mV/dec and high on/off ratio > 105 when annealing for 1hr at 600°C. The thermal diffusion process condition for this study are 1hr at 600°C and 6hr at 700°C for comparison. The annealing condition at 700oC for 6 hours shows undesired electrical characteristics against the other. Results suggests that from over thermal budget causes a plenty of Ge to precipitate against to form SiGe thin film. Annealing JAMFETs at low temperature shows outstanding Subthreshold swing and better swing condition when compared to its counterpart i.e. at higher temperature. This new process can still fabricate a comparable performance to classical planar FinFET in driving current. 

Case Studies of Brittle Interfacial Failures in Area Array Solder Interconnects

2000 ◽  
Author(s):  
George M. Wenger ◽  
Richard J. Coyle ◽  
Patrick P. Solan ◽  
John K. Dorey ◽  
Courtney V. Dodd ◽  
...  
Keyword(s):  
Failure Analysis ◽  
Case Studies ◽  
Failure Modes ◽  
Electroless Nickel ◽  
Electrical Performance ◽  
Printed Wiring Board ◽  
Solder Interconnects ◽  
Area Array ◽  
Surface Finishes ◽  
Soldering Reaction

Abstract A common pad finish on area array (BGA or CSP) packages and printed wiring board (PWB) substrates is Ni/Au, using either electrolytic or electroless deposition processes. Although both Ni/Au processes provide flat, solderable surface finishes, there are an increasing number of applications of the electroless nickel/immersion gold (ENi/IAu) surface finish in response to requirements for increased density and electrical performance. This increasing usage continues despite mounting evidence that Ni/Au causes or contributes to catastrophic, brittle, interfacial solder joint fractures. These brittle, interfacial fractures occur early in service or can be generated under a variety of laboratory testing conditions including thermal cycling (premature failures), isothermal aging (high temperature storage), and mechanical testing. There are major initiatives by electronics industry consortia as well as research by individual companies to eliminate these fracture phenomena. Despite these efforts, interfacial fractures associated with Ni/Au surface finishes continue to be reported and specific failure mechanisms and root cause of these failures remains under investigation. Failure analysis techniques and methodologies are crucial to advancing the understanding of these phenomena. In this study, the scope of the fracture problem is illustrated using three failure analysis case studies of brittle interfacial fractures in area array solder interconnects. Two distinct failure modes are associated with Ni/Au surface finishes. In both modes, the fracture surfaces appear to be relatively flat with little evidence of plastic deformation. Detailed metallography, scanning electron microscopy (SEM), energy dispersive x-ray analysis (EDX), and an understanding of the metallurgy of the soldering reaction are required to avoid misinterpreting the failure modes.

Microhardness Testing on Via Fill Material for Via In Pad Technology

2003 ◽  
Author(s):  
Norman J. Armendariz ◽  
Carolyn McCormick
Keyword(s):  
Printed Circuit Board ◽  
Failure Modes ◽  
Strong Dependence ◽  
Circuit Board ◽  
Electrical Performance ◽  
Gravimetric Analysis ◽  
Passive Components ◽  
Root Cause ◽  
Fill Material ◽  
Signal Routing

Abstract Via in pad PCB (Printed Circuit board) technology for passive components such as chip capacitors and resistors, provides the potential for improved signal routing density and reduced PCB area. Because of these improvements there is the potential for PCB cost reduction as well as gains in electrical performance through reduced impedance and inductance. However, not long after the implementation, double digit unit failures for solder joint electrical opens due to capacitor “tombstoning” began to occur. Failure modes included via fill material (solder mask) protrusion from the via as well as “out gassing” and related “tombstoning.” This failure analysis involved investigating a strong dependence on PCB supplier and, less obviously, manufacturing site. Other factors evaluated included via fill material, drill size, via fill thermal history and via fill amount or fill percent. The factor most implicated was incomplete cure of the via fill material. Previous thermal gravimetric analysis methods to determine level of polymerization or cure did not provide an ability to measure and demonstrate via fill cure level in small selected areas or its link to the failures. As a result, there was a metrology approach developed to establish this link and root-cause the failures in the field, which was based on microhardness techniques and noncontact via fill measuring metrologies.

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