scholarly journals Logic Gates Formed by Perturbations in an Asynchronous Game of Life

Symmetry ◽  
2021 ◽  
Vol 13 (5) ◽  
pp. 907
Author(s):  
Yoshihiko Ohzawa ◽  
Yukio-Pegio Gunji
Keyword(s):  
Logic Gate ◽  
Logic Gates ◽  
Logic Circuits ◽  
The Other ◽  
Probabilistic Logic ◽  
Two Dimensional ◽  
Game Of Life ◽  
The Subject ◽  
Logical Gate ◽  
Or Gate

The game of life (GL), a type of two-dimensional cellular automaton, has been the subject of many studies because of its simple mechanism and complex behavior. In particular, the construction of logic circuits using the GL has helped to extend the concept of computation. Conventional logic circuits assume deterministic transitions due to the synchronicity of the classic GL. However, they are fragile to noise and cannot maintain the expected behavior in an environment with noise. In this study, a probabilistic logic gate model was constructed using perturbations in an asynchronous game of life (AGL). Since our asynchronous automaton had no heterogeneity in either the horizontal or vertical directions, it was symmetrical with respect to spatial structure. On the other hand, the construction of the logical gate was implemented to contain heterogeneity in the horizontal or vertical directions, which could allow an AND gate and an OR gate in a single system. It was based on the phase transition between connected and unconnected phases, which is newly discovered in this study. In the model, perturbations symmetrically entail operations successful and unsuccessful, and this symmetrical double action is given not to interfere with established operations but to make operations possible. Therefore, this model had a different meaning from logic gates that exclude perturbations or use them externally. The idea of this perturbation is analogous to the inherent noise that destroys and generates structures in biological swarms.

scholarly journals Probabilistic Logic Gate in Asynchronous Game of Life with Critical Property

2021 ◽  
pp. 375-397
Author(s):  
Yukio-Pegio Gunji ◽  
Yoshihiko Ohzawa ◽  
Terutaka Tanaka
Keyword(s):  
Logic Gate ◽  
Probabilistic Logic ◽  
Critical Property ◽  
Game Of Life

Logic Devices with Spin Wave Buses - an Approach to Scalable Magneto-Electric Circuitry

2008 ◽  
Vol 1067 ◽  
Author(s):  
Alexander Khitun ◽  
Mingqiang Bao ◽  
Yina Wu ◽  
Ji-Young Kim ◽  
Augustin Hong ◽  
...  
Keyword(s):  
Spin Wave ◽  
Room Temperature ◽  
Logic Gate ◽  
Logic Gates ◽  
Logic Circuits ◽  
Logic Device ◽  
Logic Devices ◽  
Magnetic Circuits ◽  
Micrometer Scale ◽  
Magnetization Signal

ABSTRACTWe analyze spin wave-based logic circuits as a possible route to building reconfigurable magnetic circuits compatible with conventional electron-based devices. A distinctive feature of the spin wave logic circuits is that a bit of information is encoded into the phase of the spin wave. It makes possible to transmit information as a magnetization signal through magnetic waveguides without the use of an electric current. By exploiting sin wave superposition, a set of logic gates such as AND, OR, and Majority gate can be realized in one circuit. We present experimental data illustrating the performance of a three-terminal micrometer scale spin wave-based logic device fabricated on a silicon platform. The device operates in the GHz frequency range and at room temperature. The output power modulation is achieved via the control of the relative phases of two input spin wave signals. The obtained data shows the possibility of using spin waves for achieving logic functionality. The scalability of the spin wave-based logic devices is defined by the wavelength of the spin wave, which depends on the magnetic material and waveguide geometry. Potentially, a multifunctional spin wave logic gate can be scaled down to 0.1μm2. Another potential advantage of the spin wave-based logic circuitry is the ability to implement logic gates with fewer elements as compared to CMOS-based circuits in achieving same functionality. The shortcomings and disadvantages of the spin wave-based devices are also discussed.

scholarly journals Penerapan Teknologi Augmented Reality Untuk Pembelajaran Gerbang Logika Pada Mata Pelajaran Sistem Komputer

2020 ◽  
Vol 4 (3) ◽  
pp. 503
Author(s):  
Mochammad Machlul Alamin ◽  
Hendrawan Armanto ◽  
Indra Maryati
Keyword(s):  
Augmented Reality ◽  
Logic Gate ◽  
Computer Systems ◽  
Logic Gates ◽  
Post Test ◽  
Augmented Reality Technology ◽  
The Subject ◽  
Power Point ◽  
Inputs And Outputs ◽  
Learning Logic

Logic Gate is one of the materials in the subject of Computer Systems at the level of SMK in class X. However, until now the learning media only uses textbooks, power point slides and manual simulations using blackboards. While the material about logic gates is very difficult if it is not directly simulated because it is directly related to the interaction of inputs and outputs at each logic gate. During the use of textbooks and manual simulation media students find it difficult to understand the material about this logic gate. The advantage of learning that utilizes augmented reality is an attractive display and displays 3D logic gate objects and input buttons that can be used to interact directly and the output is also in the form of 3D lamp objects, with this augmented reality technology will be very helpful and useful for simulating the gate logic is directly and easily understood by students. 3D logic gate animations are created using the 3D Blender application and the Augmented Reality process is created using the Unity and Vuforia SDK Library. This logic gate learning application has been applied to two classes, namely the control class and the experimental class. From the results of the Pre Test and Post Test that have been done, the control class has a 22.0% increase in percentage, while the experimental class has a 33.4% increase in percentage. Thus the learning application that utilizes Augmented Reality technology can be applied as a medium for learning logic gates at the vocational level of class X

Performance Evaluation of Two Dimensional Photonic Crystal Based All Optical AND/OR Logic Gates

2018 ◽  
Vol 0 (0) ◽  
Author(s):  
Jayson K Jayabarathan ◽  
G Subhalakshmi ◽  
S Robinson
Keyword(s):  
Photonic Crystal ◽  
Contrast Ratio ◽  
Logic Gates ◽  
Two Dimensional ◽  
Bit Rate ◽  
Dimensional Photonic Crystal ◽  
Response Period ◽  
Two Dimensional Photonic Crystal ◽  
Reference Input ◽  
Or Gate

AbstractIn this paper, OR and AND logic gate functions are realized in a triangular lattice using two dimensional photonic crystal (2DPC). The proposed design of logic gates are based on the phenomenon of resonance and interference. The OR and AND logic gates are constructed by varying the rod radius and by creating Y-shaped waveguide in the structure. Initially, the OR gate is designed with reference input and without reference input and it’s extended for AND gate. The functional parameters of the logic gates such as response period, bit rate, contrast ratio and field distribution of different logics are investigated through 2D finite difference time domain (FDTD) method. The contrast ratio, response period, bit rate and size of the three input OR gate are 30 dB, 0.52 ps, 1.92 Tbps and 12.6 μm×11 μm, respectively. Similarly, the aforementioned parameters are estimated for two input OR gate, two input AND gate and three input AND gate. The proposed logic gates are highly desirable for integrated optics.

scholarly journals PROTOYPE GERBANG LOGIKA ( AND, OR, NOT, NAND, NOR ) PADA LABORATORIUM ELEKTRONIKA STMIK ROYAL KISARAN

2017 ◽  
Vol 1 (1) ◽  
pp. 37
Author(s):  
Helmi Fauzi Siregar ◽  
Ikhsan Parinduri
Keyword(s):  
Learning Process ◽  
Teaching And Learning ◽  
Logic Gate ◽  
Logic Gates ◽  
Digital Circuit ◽  
Nand Gate ◽  
Abstract Logic ◽  
Working Principle ◽  
Input Gate ◽  
Or Gate

Abstract - Logic gate prototype aims to meet the needs and smoothness of the teaching and learning process in one of the digital circuit lecture materials. Proof of the logic of OR, AND, NOT, NOR, and NAND gates. The working principle of logic gate prototype is working based on input logic including 0 and 1. For AND logic gates are input multiplication gates consisting of (0,0, 0,1, 1,0, 1,1) and output consists of 1 for high (1) and 3 for low (0). For OR gate is the input sum gate consists of (0,0, 0,1, 1,0, 1,1) and the output consists of 3 high (1) and 1 low (0). For the NAND gate is the logic inverting gate of the AND input gate consisting of (0,0, 0,1, 1,0, 1,1) and the output consists of 3 high (1) and 1 low (0). For NOR input logic gate consists of (0,0, 0,1, 1,0, 1,1) and the output consists of 1 for high (1) and 3 for low (0). For the NOT gate is the inverse gate with input (1, 0) and the output consists of (0,1). Keywords - Logic Gate, Prototype, OR, AND, NOT, NOR, NAND

NMOS Logic Circuits Using 4H-SiC MOSFETs for High Temperature Applications

2010 ◽  
Vol 645-648 ◽  
pp. 1143-1146 ◽  
Author(s):  
Martin Le-Huu ◽  
Frederik F. Schrey ◽  
Michael Grieb ◽  
H. Schmitt ◽  
Volker Haeublein ◽  
...  
Keyword(s):  
High Temperature ◽  
Dielectric Breakdown ◽  
Logic Gate ◽  
Logic Gates ◽  
Logic Circuits ◽  
Constant Voltage ◽  
Gate Operation ◽  
Operating Field ◽  
Voltage Stress ◽  
High Temperature Operation

Normally-off 4H-SiC MOSFETs are used to build NMOS logic gates intended for high temperature operation. The logic gates are characterized between 25°C and 500°C. Stable gate operation for more than 200h at 400°C in air is demonstrated. The excellent MOS reliability is quantified using I-V curves to dielectric breakdown and constant voltage stress to breakdown at 400°C. Although the effective tunneling barrier height B for electrons lowers to 2eV at 400°C, the extrapolated lifetime from constant voltage stress to breakdown measurements is longer than 105h at 400°C for typical logic gate operating field strength of 2MV/cm.

scholarly journals Mobile Virtual Reality to Develop a Virtual Laboratorium for the Subject of Digital Engineering

2019 ◽  
Vol 13 (04) ◽  
pp. 80
Author(s):  
Khairudin M ◽  
Triatmaja A.K ◽  
Istanto W.J ◽  
Azman M.N.A
Keyword(s):  
Virtual Reality ◽  
Logic Gate ◽  
Logic Gates ◽  
Virtual Laboratory ◽  
Virtual Reality Technology ◽  
Learning And Teaching ◽  
Virtual Tools ◽  
Engineering Theory ◽  
The Subject ◽  
Digital Engineering

This paper provides development of a virtual laboratorium for the subject of digital engineering. The virtual digital engineering laboratory based on mobile virtual reality is a finding that can be used for replacing a real laboratory. Using a virtual laboratory can be conducted a learning and teaching process at anytime and anywhere as long as it has an android device. This study applies a virtual laboratory to mobile virtual reality for a virtual digital engineering laboratory. The results of this study were fuctional application software to learn how to apply a virtual digital engineering laboratory through mobile virtual reality technology. A lot of components and circuits of logic gate can be simulated in this virtual laboratorium. This study presents a simple Android-based virtual tools for the visualization and investigation  in real time of circuits of logic gates without signal disturbances. The package can be used as an educational tool in various lectures or homework to aid teaching digital engineering theory or practically.

scholarly journals A New Systematic Encoding  Circuit of Hamming (15, 11) Using Low-Power XOR-FS-GDI Based Logic Gate: Fast Computing and Efficient Area FEC

2021 ◽  
Author(s):  
Mohsen El-Bendary ◽  
O El-Badry
Keyword(s):  
Low Power ◽  
Delay Time ◽  
Power Efficiency ◽  
Logic Gate ◽  
Logic Gates ◽  
The Other ◽  
Simulation Experiments ◽  
Hamming Codes ◽  
Communications Systems ◽  
Other Hand

Abstract Due to the power efficiency importance of digital signal processing and data protection in different communications systems, this paper proposes an efficient design of different Hamming Codes utilizing Full Swing- Gate Diffusion Input (FS-GDI) approach. The proposed codes design aims to improve the power efficiency and the required area through reducing the required number of transistors. FS-GDI is a new low power VLSI design approach, it is a power effective approach for realizing the different logic gates. In this work, the Hamming codes (11, 7) and (15, 11) are designed by utilizing the original GDI, FS-GDI and the traditional CMOS approaches. The amount of consumed power, delay time, Power Delay Product (PDP) and hardware simplicity-Number of Transistors (No. Ts) are employed as a metrics for evaluating the efficiency of the proposed design compared to the traditional design. The design simulation experiments are executed utilizing Cadence Virtuoso simulator package under 65nm technology. The simulation experiments revealed these proposed codes achieve delay time reduction by 52.91% and 10% for Hamming codes (7, 4) and (11, 7), respectively On the other hand, the Hardware (H/W) of these codes became more simple where the H/W simplicity of the used Hamming codes is reduced 50 % CMOS approaches respectively. From the results analysis, the proposed design achieves efficient power and the delay optimizing of Hamming codes utilizing the FS-GDI approach. On the other hand, the power consumption and area in communications systems due to the encoding process can be reduces.

Design of Universal Logic Gates Using Homo and Hetero-Junction Double Gate TFETs with Pseudo-Derived Logic

2021 ◽  
Author(s):  
Lokesh B ◽  
Sai Pavan kumar K ◽  
Pown M ◽  
Lakshmi B
Keyword(s):  
Power Consumption ◽  
Logic Gate ◽  
Logic Gates ◽  
Propagation Delay ◽  
Logic Circuits ◽  
Logic Circuit ◽  
Nand Gate ◽  
Double Gate ◽  
Nor Gate ◽  
Nor Logic Gate

Abstract This work explores homo and hetero-junction Tunnel field-effect transistor (TFET) based NAND and NOR logic circuits using 30 nm technology and compares their performance in terms of power consumption and propagation delay. By implementing homo-junction TFET based NAND and NOR logic circuits, it has been observed that NAND consumes less power than NOR gate, since current drawn by PTFET in pull-up network of NOR gate is higher. The delay of homo-junction TFET based NOR logic gate is lesser than that of NAND gate due to its reduced internal capacitances. To meet the enhanced performance of both NAND and NOR logic circuits, shorted and independent double gate hetero-junction (GaSb-InAs) TFETs are designed and implemented. In order to reduce both power consumption and delay further, Pseudo-derived logic is implemented in NAND and NOR logic circuits for the first time. Hetero-junction TFET based NAND with Pseudo-derived logic circuit shows lesser propagation delay of 103 times and reduction in power consumption by 0.75 times compared to hetero-junction NAND logic circuit. Hetero-junction TFET based NOR with Pseudo-derived logic shows that the reduction in power consumption is of 103 times and less propagation delay than that of hetero-junction NOR logic circuit

scholarly journals Ultra-fast and compact all-optical encoder based on photonic crystal nano-resonator without using nonlinear materials

2019 ◽  
Vol 11 (1) ◽  
pp. 10 ◽  
Author(s):  
Saeed Olyaee
Keyword(s):  
Photonic Crystal ◽  
Photonic Crystals ◽  
Quantum Electronics ◽  
Logic Gate ◽  
Logic Gates ◽  
Ring Resonators ◽  
Two Dimensional ◽  
Optical Logic ◽  
Optical Encoder ◽  
All Optical

In this paper an ultra-compact all-optical encoder is presented by using a two-dimensional photonic crystal. The designed logic gate is based on the interference effect. The proposed structure consists of several photonic crystal waveguides connected by 2 nano-resonators. The nano-resonators are designed to reduce the size of the radius of the dielectric rods. The contrast ratios and delay time for the proposed all-optical encoder are respectively 6 dB and 125 fs. The size of the structure is equal to 132 µm2. Equality of the output power in the logic states “one”, the small dimensions, the low delay time, compact and simple structure have shown that the logic gate is suitable for the using in optical integrated circuits. Full Text: PDF ReferencesA. Salmanpour, Sh. Mohammadnejad, A. Bahrami, "Photonic crystal logic gates: an overview", Optical and Quantum Electronics. 47, 2249 (2015). CrossRef S. C. Xavier, B. E. Carolin, A. p. Kabilan, W. Johnson, "Compact photonic crystal integrated circuit for all-optical logic operation", IET Optoelectronics. 10, 142 (2016). CrossRef Y. Miyoshi, K. Ikeda, H. Tobioka, T. Inoue, S. Namiki, K. Kitayama, "Ultrafast all-optical logic gate using a nonlinear optical loop mirror based multi-periodic transfer function", Optics Express. 16, 2570 (2008). CrossRef D. K. Gayen, A. Bhattachryya, T. Chattopadhyay, J. N. Roy, "Ultrafast All-Optical Half Adder Using Quantum-Dot Semiconductor Optical Amplifier-Based Mach-Zehnder Interferometer", Journal of Lightwave Technology. 30, 3387 (2012). CrossRef A. Mohebzadeh-Bahabady, S. Olyaee, "All-optical NOT and XOR logic gates using photonic crystal nano-resonator and based on an interference effect", IET Optoelectronics. 12, 191 (2018). CrossRef Z. Mohebbi, N. Nozhat, F. Emami, "High contrast all-optical logic gates based on 2D nonlinear photonic crystal", Optics Communications. 355, 130 (2015). CrossRef M. Mansouri-Birjandi, M. Ghadrdan, "Full-optical tunable add/drop filter based on nonlinear photonic crystal ring resonators", Photonics and Nanostructures-Fundamentals and Applications. 21, 44 (2016). CrossRef H. Alipour-Banaei, S. Serajmohammadi, F. Mehdizadeh, "Effect of scattering rods in the frequency response of photonic crystal demultiplexers", Journal of Optoelectronics and Advanced Materials. 17, 259 (2015). DirectLink A. Mohebzadeh-Bahabady, S. Olyaee, H. Arman, "Optical Biochemical Sensor Using Photonic Crystal Nano-ring Resonators for the Detection of Protein Concentration", Current Nanoscience. 13, 421 (2017). CrossRef S. Olyaee, A. Mohebzadeh-Bahabady, "Designing a novel photonic crystal nano-ring resonator for biosensor application", Optical and Quantum Electronics. 47, 1881 (2015). CrossRef F. Parandin, R. Malmir, M. Naseri, A. Zahedi, "Reconfigurable all-optical NOT, XOR, and NOR logic gates based on two dimensional photonic crystals", Superlattices and Microstructures. 113, 737 (2018). CrossRef F. Mehdizadeh, M. Soroosh, H. Alipour-Banaei, "Proposal for 4-to-2 optical encoder based on photonic crystals", IET Optoelectronics. 11, 29 (2017). CrossRef M. Hassangholizadeh-Kashtiban, R. Sabbaghi-Nadooshan, H. Alipour-Banaei, "A novel all optical reversible 4 × 2 encoder based on photonic crystals", Optik. 126, 2368 (2015). CrossRef T. A. Moniem, "All-optical digital 4 × 2 encoder based on 2D photonic crystal ring resonators", Journal of Modern Optics. 63, 735 (2016). CrossRef S. Gholamnejad, M. Zavvari, "Design and analysis of all-optical 4–2 binary encoder based on photonic crystal", Optical and Quantum Electronics. 49, 302 (2017). CrossRef H. Seif-Dargahi, "Ultra-fast all-optical encoder using photonic crystal-based ring resonators", Photonic Network Communications. 36, 272 (2018). CrossRef S. Olyaee, M. Seifouri, A. Mohebzadeh-Bahabady, and M. Sardari, "Realization of all-optical NOT and XOR logic gates based on interference effect with high contrast ratio and ultra-compacted size", Optical and Quantum Electronics. 50, 12 (2018). CrossRef C. J. Wu, C. P. Liu, Z. Ouyang, "Compact and low-power optical logic NOT gate based on photonic crystal waveguides without optical amplifiers and nonlinear materials", Applied Optics.51, 680 (2012). CrossRef Y. C. Jiang, S. B. Liu, H. F. Zhang, X. K. Kong. "Realization of all optical half-adder based on self-collimated beams by two-dimensional photonic crystals", Optics Communications. 348, 90 (2015). CrossRef A. Salmanpour, S. Mohammadnejad, P. T. Omran, "All-optical photonic crystal NOT and OR logic gates using nonlinear Kerr effect and ring resonators", Optical and Quantum Electronics. 47, 3689 (2015). CrossRef E. H. Shaik, N. Rangaswamy, "Single photonic crystal structure for realization of NAND and NOR logic functions by cascading basic gates", Journal of Computational Electronics. 17, 337 (2018). CrossRef

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