scholarly journals ZDC: A Zone Data Compression Method for Solid State Drive Based Flash Memory

Symmetry ◽  
2020 ◽  
Vol 12 (4) ◽  
pp. 623
Author(s):  
Xin Ye ◽  
Zhengjun Zhai ◽  
Xiaochang Li
Keyword(s):  
Solid State ◽  
Data Compression ◽  
Data Storage ◽  
Flash Memory ◽  
Research Result ◽  
Nand Flash ◽  
Data Deduplication ◽  
Solid State Drive ◽  
Research Results ◽  
Hot Zone

Solid-state drive (SSD) with flash memory as the storage medium are being widely used in various data storage systems. SSD data compression means that data is compressed before it is written to Not-And (NAND) Flash. Data compression can reduce the amount of data written in NAND Flash and improve the performance and reliability of SSDs. At present, the main problem facing data compression of SSD is how to improve the efficiency of data compression and decompression. In order to improve the performance of data compression and decompression, this study proposes a method of SSD data deduplication based on zone division. First, this study divides the storage space of the SSD into zones and divides them into one hot zone and multiple cold zones according to the different erasing frequency. Second, the data in each zone is divided into hot data and cold data according to the number of erasures. At the same time, the address mapping table in the hot zone is loaded into the cache. Finally, when there is a write or read request, the SSD will selectively compress or decompress the data according to the type of different zones. Through simulation tests, the correctness and effectiveness of this study are verified. The research results show that the data compression rate of this research result can reach 70–95%. Compared with SSD without data compression, write amplification is reduced by 5 to 30%, and write latency is reduced by 5 to 25%. The research results have certain reference value for improving the performance and reliability of SSD.

A Novel Bit-Flipping LDPC Decoder for Solid-State Data Storage

2014 ◽  
Vol 513-517 ◽  
pp. 2094-2098 ◽  
Author(s):  
Wen Zhe Zhao ◽  
Kai Zhao ◽  
Qiu Bo Chen ◽  
Min Jie Lv ◽  
Zuo Xun Hou
Keyword(s):  
Solid State ◽  
Error Correction ◽  
Data Storage ◽  
Flash Memory ◽  
Message Passing ◽  
High Speed ◽  
Design Solution ◽  
Nand Flash ◽  
Nand Flash Memory ◽  
State Data

This paper concerns the design of high-speed and low-cost LDPC code bit-flipping decoder. Due to its inferior error correction strength, bit-flipping decoding received very little attention compared with message-passing decoding. Nevertheless, emerging flash-based solid-state data storage systems inherently favor a hybrid bit-flipping/message-passing decoding strategy, due to the significant dynamics and variation of NAND flash memory raw storage reliability. Therefore, for the first time highly efficient silicon implementation of bit-flipping decoder becomes a practically relevant topic. To address the drawbacks caused by the global search operation in conventional bit-flipping decoding, this paper presents a novel bit-flipping decoder design. Decoding simulations and ASIC design show that the proposed design solution can achieve upto 80% higher decoding throughput and meanwhile consume upto 50% less silicon cost, while maintaining almost the same decoding error correction strength.

A New Write Caching Algorithm for Solid State Disks

2011 ◽  
Vol 341-342 ◽  
pp. 700-704
Author(s):  
Bai Yi Huang
Keyword(s):  
Solid State ◽  
Data Storage ◽  
Flash Memory ◽  
Theory And Practice ◽  
Solid State Disks ◽  
Storage Technology ◽  
Mechanical Devices ◽  
Storage Technologies ◽  
A Performance

Flash-based solid state disks (SSD) is a performance based data storage technology that optimizes the use of flash-based technology to implement its data storage capabilities compared with mechanically available data storage technologies. It has been argued in theory and practice that SSD devices are better performers compared with mechanical devices. To improve the efficiency of a flash memory SSD device, it is important for it to be designed to be computationally support parallel operations.

23% Higher Performance 2D MLC/3D TLC NAND Flash Hybrid Solid-State Drive

2017 ◽  
Author(s):  
Y. Sakaki ◽  
T. Yamada ◽  
C. Matsui ◽  
Y. Yamaga ◽  
K. Takeuchi
Keyword(s):  
Solid State ◽  
Nand Flash ◽  
Solid State Drive

NAND Flash Memory/ReRAM Hybrid Unified Solid-State-Storage Architecture

2014 ◽  
Vol 61 (4) ◽  
pp. 1119-1132 ◽  
Author(s):  
Shuhei Tanakamaru ◽  
Masafumi Doi ◽  
Ken Takeuchi
Keyword(s):  
Solid State ◽  
Flash Memory ◽  
Nand Flash ◽  
Nand Flash Memory

Non Volatile Memory Technologies: Floating Gate Concept Evolution

2004 ◽  
Vol 830 ◽  
Author(s):  
Cesare Clementi ◽  
Roberto Bez
Keyword(s):  
Data Storage ◽  
Flash Memory ◽  
Floating Gate ◽  
Nand Flash ◽  
Know How ◽  
Technology Node ◽  
Cell Architecture ◽  
Non Volatile Memory ◽  
Volatile Memory ◽  
The Cost

ABSTRACTThe most relevant phenomenon of this last decade in the field of semiconductor memories has been the explosive growth of the Flash memory market, driven by cellular phones and other types of electronic portable equipments (palm top, mobile PC, mp3 audio player, digital camera and so on). Moreover, in the coming years portable systems will ask even more non volatile memories either with high density and very high writing throughput for data storage application, or with fast random access for code execution in place. The strong consolidated know-how (more than ten years of experience), the flexibility and the cost make the floating gate Flash Memory a largely utilized, well-consolidated and mature technology for most of the non-volatile memory application. Today Flash sales represent a considerable amount of the overall semiconductor market.Nowadays two of the several cell architecture proposed up to now can be considered as industry standard: the common ground NOR Flash that due to its versatility is addressing both the code and data storage segments and the NAND Flash, optimized for the data storage market.The exploitation of the multilevel approach at each technology node allows the increase of the memory efficiency, about doubling the density at the same chip size, widening the application range and reducing the cost per bit.In this paper the main issues related to both NOR and NAND Flash memory technology will be summarized, with the aim of describing both the basic functionality of the memory cell and the main cell architecture today consolidated. Both cells are basically a floating-gate MOS transistor, programmed by channel hot electron (NOR) or by Fowler-Nordheim tunneling (NAND) and erased by Fowler-Nordheim tunnel. The main reliability properties, charge retention and endurance, are presented, together with some comments on the basic physical mechanisms responsible for.A couple of innovative approaches to floating gate cell evolution, namely nanocrystal memory and 3-D cell will be described.Finally the Flash cell scaling issues will be covered, pointing out the main challenges. The Flash cell scaling has been demonstrated to be really possible and to be able to follow the Moore's law down to the 90 nm technology generations. The technology development and the consolidated know-how are expected to sustain the scaling trend down to the 50 nm technology node and below as forecasted by the ITRS roadmap.

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