scholarly journals Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

Sensors ◽  
2008 ◽  
Vol 8 (11) ◽  
pp. 7438-7452 ◽  
Author(s):  
Azrul Hamzah ◽  
Jumril Yunas ◽  
Burhanuddin Majlis ◽  
Ibrahim Ahmad
Keyword(s):  
Mems Devices ◽  
Wafer Level ◽  
Capacitive Accelerometer ◽  
Wafer Level Packaging

Wafer Level Micropackaging of MEMS Devices Using Thin Film Anodic Bonding

2002 ◽  
Vol 729 ◽  
Author(s):  
Lauren E. S. Rohwer ◽  
Andrew D. Oliver ◽  
Melissa V. Collins
Keyword(s):  
Shear Strength ◽  
Test Sample ◽  
Anodic Bonding ◽  
Mems Devices ◽  
Wafer Level ◽  
Thermal Actuators ◽  
Wafer Level Packaging ◽  
Hermetic Seal ◽  
Leak Testing ◽  
Before And After

AbstractA wafer level packaging technique that involves anodic bonding of Pyrex wafers to released surface micromachined wafers is demonstrated. Besides providing a hermetic seal, this technique allows full wafer release, provides protection during die separation, and offers the possibility of integration with optoelectronic devices. Anodic bonding was performed under applied voltages up to 1000 V, and temperatures ranging from 280 to 400°C under vacuum (10-4Torr). The quality of the bonded interfaces was evaluated using shear strength testing and leak testing. The shear strength of Pyrex-to-polysilicon and aluminum bonds was ∼10-15 MPa. The functionality of surface micromachined polysilicon devices was tested before and after anodic bonding. 100% of thermal actuators, 94% of torsional ratcheting actuators, and 70% of microengines functioned after bonding. The 70% yield was calculated from a test sample of 25 devices.

On Hermeticity Detection of Wafer Level Packages for MEMS Devices

2005 ◽  
Author(s):  
A. Goswami ◽  
B. Han ◽  
C. Wade ◽  
A. Chien
Keyword(s):  
Mems Devices ◽  
Rate Measurement ◽  
Wafer Level ◽  
Measurement Sensitivity ◽  
Leak Test ◽  
Design Assessment ◽  
Hermetic Packaging ◽  
Wafer Level Packaging ◽  
Test Parameters ◽  
Leak Testing

Wafer level packaging has emerged as one of the promising solutions for hermetic packaging of MEMS devices. Detection of the level of hermeticity of the package is essential for reliability and design assessment of the devices. Traditionally, hermeticity has been tested using Helium based fine leak testing. However, there are limitations when this technique is used for the hermeticity detection of small volumes (< 10−3 cc) that are typical in wafer level packages. This paper reviews the helium fine leak test, its limitations and the influence of the different test parameters on leakage rate measurement are analyzed for wafer level packages with small cavity volumes. The results indicate a need for development of a new hermeticity measurement technique to achieve the measurement sensitivity required for wafer level packages.

Ceramic Via Wafer-Level Packaging for MEMS

2005 ◽  
Author(s):  
John M. Heck ◽  
Leonel R. Arana ◽  
Bill Read ◽  
Thomas S. Dory
Keyword(s):  
Mems Devices ◽  
Wafer Level ◽  
Micro Electro Mechanical Systems ◽  
Mems Switches ◽  
Mems Packaging ◽  
Wafer Level Packaging ◽  
Novel Approach ◽  
Electrical Interconnection ◽  
Tin Silver Copper ◽  
Board Level

We will present a novel approach to wafer level packaging for micro-electro-mechanical systems. Like most common MEMS packaging methods today, our approach utilizes a wafer bonding process between a cap wafer and a MEMS device wafer. However, unlike the common methods that use a silicon or glass cap wafer, our approach uses a ceramic wafer with built-in metal-filled vias, that has the same size and shape as a standard 150 mm silicon wafer. This ceramic via wafer packaging method is much less complex than existing methods, since it provides hermetic encapsulation and electrical interconnection of the MEMS devices, as well as a solderable interface on the outside of the package for board-level interconnection. We have demonstrated successful ceramic via wafer-level packaging of MEMS switches using eutectic gold-tin solder as well as tin-silver-copper solder combined with gold thermo-compression bonding. In this paper, we will present the ceramic via MEMS package architecture and discuss the associated bonding and assembly processes.

Wafer Bonding Processes for the Manufacture of Microsystems

2008 ◽  
Author(s):  
Tony Rogers ◽  
Nick Aitken
Keyword(s):  
Bond Strength ◽  
Wafer Bonding ◽  
High Efficiency ◽  
Glass Frit ◽  
Acoustic Microscopy ◽  
Anodic Bonding ◽  
High Yield ◽  
Mems Devices ◽  
Wafer Level ◽  
Wafer Level Packaging

Wafer bonding is a widely used step in the manufacture of Microsystems, and serves several purposes: • Structural component of the MEMS device. • First level packaging. • Encapsulation of vacuum or controlled gas. In addition the technology is becoming more widely used in IC fabrication for wafer level packaging (WLP) and 3D integration. It is also widely used for the fabrication of micro fluidic structures and in the manufacture of high efficiency LED’s. Depending on the application, temperature constraints, material compatibility etc. different wafer bonding processes are available, each with their own benefits and drawbacks. This paper describes various wafer bonding processes that are applicable, not only to silicon, but other materials such as glass and quartz that are commonly used in MEMS devices. The process of selecting the most appropriate bonding process for the particular application is presented along with examples of anodic, glass frit, eutectic, direct, adhesive and thermo-compression bonding. The examples include appropriate metrology for bond strength and quality. The paper also addresses the benefits of being able to treat the wafer surfaces in-situ prior to bonding in order to improve yield and bond strength, and also discusses equipment requirements for achieving high yield wafer bonding, along with high precision alignment accuracy, good force and temperature uniformity, high wafer throughput, etc. Some common problems that can affect yield are identified and discussed. These include local temperature variations, that can occur with anodic bonding, and how to eliminate them; how to cope with materials of different thermal expansion coefficient; how best to deal with out-gassing and achieve vacuum encapsulation; and procedures for multi-stacking wafers of differing thicknesses. The presentation includes infra-red and scanning acoustic microscopy images of various bond types, plus some examples of what can go wrong if the correct manufacturing protocol is not maintained.

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