scholarly journals High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1451
Author(s):  
Asep Muhamad Awaludin ◽  
Harashta Tatimma Larasati ◽  
Howon Kim
Keyword(s):  
Elliptic Curve ◽  
Digital Signal Processor ◽  
Execution Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Digital Signal ◽  
Low Complexity ◽  
Montgomery Ladder ◽  
Modular Multiplier ◽  
Pipelined Multiplier

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

scholarly journals High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

2021 ◽  
Author(s):  
Asep Muhamad Awaludin ◽  
Harashta Tatimma Larasati ◽  
Howon Kim
Keyword(s):  
Elliptic Curve ◽  
Elliptic Curve Cryptography ◽  
Execution Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Low Complexity ◽  
Multiplication Algorithm ◽  
Montgomery Ladder ◽  
Modular Multiplier ◽  
Pipelined Multiplier

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes DSP primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020, yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

scholarly journals High-Speed CurrentdqPI Controller for Vector Controlled PMSM Drive

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Mohammad Marufuzzaman ◽  
Mamun Bin Ibne Reaz ◽  
Labonnah Farzana Rahman ◽  
Tae Gyu Chang
Keyword(s):  
Digital Signal Processor ◽  
Execution Time ◽  
High Speed ◽  
Modular Design ◽  
Permanent Magnet Synchronous Motor ◽  
Digital Signal ◽  
Implementation Cost ◽  
Current Controller ◽  
Field Programmable ◽  
Improved Accuracy

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Currentdqcontroller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed currentdqPI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era.

scholarly journals Detection and control of a gyroscopically induced vibration to improve the balance of a single-wheel robot

2017 ◽  
Vol 37 (3) ◽  
pp. 443-455 ◽  
Author(s):  
Sangdeok Lee ◽  
Seul Jung
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Balance Control ◽  
A Priori ◽  
Experimental Studies ◽  
Notch Filter ◽  
Digital Signal ◽  
Control Performance ◽  
And Control ◽  
Balancing Control

In this article, an experimental investigation of the detection of a gyroscopically induced vibration and the balancing control performance of a single-wheel robot is presented. The balance of the single-wheel robot was intended to be maintained by virtue of the gyroscopic effect induced from a highly rotating flywheel. Since the flywheel rotates at a high speed, an asymmetrical structure of a flywheel causes an irregular rotation and becomes one of the major vibration sources. A vibration was detected and suppressed a priori before applying control algorithms to the robot. Gyroscopically induced vibrations can empirically be detected with different rotational velocities. The detection of the balancing angle of the single-wheel robot was accomplished by using an attitude and heading reference system. After identifying the vibrating frequencies, a notch filter was designed to suppress the vibration at the typical frequencies identified through experiments. A digital filter was designed and implemented in a digital signal processor(DSP) along with the control scheme for the balance control performance. The performance of the proposed method was verified by the experimental studies on the balancing control of the single-wheel robot. Experimental results confirmed that the notch filter designed following the detection of the flywheel’s vibration actually improved the balancing control performance. A half of the vibration magnitude was reduced by the proposal.

A Polarization Stabilization Control System Based on DSP

2014 ◽  
Vol 631-632 ◽  
pp. 806-810 ◽  
Author(s):  
Qing Xiang Hou ◽  
Xue Guang Yuan ◽  
Yan Gan Zhang ◽  
Jin Nan Zhang
Keyword(s):  
Control System ◽  
Digital Signal Processor ◽  
High Speed ◽  
Particle Swarm Optimization Algorithm ◽  
Low Frequency ◽  
Digital Signal ◽  
Rf Power ◽  
Swarm Optimization ◽  
Modified Particle Swarm Optimization ◽  
Stabilization Control

A polarization stabilization control system based on digital signal processor (DSP) is proposed in this paper. The system uses low frequency radio frequency (RF) power as control signal for polarization stabilization, and it does not need high-speed circuit to track fast polarization change. Modified particle swarm optimization algorithm is utilized and the effectiveness of polarization stabilization control is experimentally verified.

scholarly journals Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

2021 ◽  
Author(s):  
Markeljan Fishta ◽  
Franco Fiori
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Experimental Tests ◽  
General Purpose ◽  
Data Conversion ◽  
Clock Frequency ◽  
Main Challenge ◽  
Modulated Signals

Abstract$$\varDelta \varSigma $$ Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone $$\varDelta \varSigma $$ Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of $$\varDelta \varSigma $$ Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few $$\hbox {MHz}$$ MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

Low Power, High Speed and Area Efficient Binary Count Multiplier

2016 ◽  
Vol 25 (04) ◽  
pp. 1650027 ◽  
Author(s):  
Kore Sagar Dattatraya ◽  
Belgudri Ritesh Appasaheb ◽  
Ramdas Bhanudas Khaladkar ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Digital Signal Processor ◽  
Word Length ◽  
High Speed ◽  
Digital Signal ◽  
General Purpose ◽  
Computation Method ◽  
Partial Product ◽  
Wallace Tree ◽  
Power Delay Product ◽  
Binary Count

Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

Design and Implementation of Audio Process System Based on DSP

2014 ◽  
Vol 945-949 ◽  
pp. 1752-1755
Author(s):  
Chui Xin Chen ◽  
Yang Hong Mao
Keyword(s):  
Real Time ◽  
Digital Signal Processor ◽  
High Speed ◽  
Audio Signal ◽  
Reference Value ◽  
Digital Signal ◽  
Real Time Processing ◽  
Audio Processing ◽  
Time Processing ◽  
Process System

The real-time processing for the input analog audio signal, audio processing program is proposed based on DSP. The system use FFT algorithm as the core, first, the input analog audio signal is sampled and A/D conversion using TLV320AIC23, and then use high speed digital signal processor to make real-time processing for the signal. Theoretical and experimental results show that the system can meet the design requirements, it has the advantage of high real-time and simple structure. The system has a good application and reference value for the development and design of data collecting and remote monitoring.

scholarly journals High Speed PSO Micro-Pipelined Adder

2020 ◽  
Vol 8 (5) ◽  
pp. 4073-4079
Keyword(s):  
Digital Signal Processor ◽  
Power Dissipation ◽  
High Speed ◽  
Continuous Monitoring ◽  
Digital Signal ◽  
Propagation Delay ◽  
Wearable Devices ◽  
Data Path ◽  
Processing Data ◽  
Cost Utilization

For continuous monitoring of individual wellbeing, wearable devices are indispensable. The limitations of cost, utilization of power, delay and restricted device measurements are the basic issues which should be dealt cautiously while designing these battery powered devices. The wearables use high-end processors dedicated for complicated signal processing. Data path plays a key role in every digital signal processor. Adder is the most widely used component in wearable technology. This work proposes a novel architecture for PS0 pipelined adder. The proposed adder is implemented in 65nm TSMC CMOS and its performance has been compared with state-of-art adders. The SPICE level simulations are performed on HSPICE using 65nm TSMC CMOS @ 1.2 V. All the designs have been simulated with extracted wire and layout parasitics. The proposed adder ensures the lowest propagation delay which is 79.33% less when compared to RCA and has a power dissipation of 0.225 mw which is 25.4 % less as compared to CLA. Besides, the proposed adder offers a benefit of having lower transistor count which is 49.6% less as compared to RCA.

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