scholarly journals High-Speed CurrentdqPI Controller for Vector Controlled PMSM Drive

2014 ◽  
Vol 2014 ◽  
pp. 1-9 ◽  
Author(s):  
Mohammad Marufuzzaman ◽  
Mamun Bin Ibne Reaz ◽  
Labonnah Farzana Rahman ◽  
Tae Gyu Chang
Keyword(s):  
Digital Signal Processor ◽  
Execution Time ◽  
High Speed ◽  
Modular Design ◽  
Permanent Magnet Synchronous Motor ◽  
Digital Signal ◽  
Implementation Cost ◽  
Current Controller ◽  
Field Programmable ◽  
Improved Accuracy

High-speed current controller for vector controlled permanent magnet synchronous motor (PMSM) is presented. The controller is developed based on modular design for faster calculation and uses fixed-point proportional-integral (PI) method for improved accuracy. Currentdqcontroller is usually implemented in digital signal processor (DSP) based computer. However, DSP based solutions are reaching their physical limits, which are few microseconds. Besides, digital solutions suffer from high implementation cost. In this research, the overall controller is realizing in field programmable gate array (FPGA). FPGA implementation of the overall controlling algorithm will certainly trim down the execution time significantly to guarantee the steadiness of the motor. Agilent 16821A Logic Analyzer is employed to validate the result of the implemented design in FPGA. Experimental results indicate that the proposed currentdqPI controller needs only 50 ns of execution time in 40 MHz clock, which is the lowest computational cycle for the era.

Improving the Dynamic Response during Field Weakening Control of IPMSM Drive System using Adaptive Hysteresis Current Control Technique

2016 ◽  
Vol 17 (3) ◽  
pp. 235-249 ◽  
Author(s):  
Amiya Naik ◽  
Anup Kumar Panda ◽  
Sanjeeb Kumar Kar
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Digital Signal ◽  
Torque Ripple ◽  
Current Control ◽  
Control Technique ◽  
Switching Frequency ◽  
Motor Speed ◽  
Current Controller ◽  
Current Error

Abstract This paper presents the control of IPMSM drive in flux weakening region, for high speed applications. An adaptive hysteresis band current controller has been designed and implemented in this work to overcome the drawbacks which are present in case of conventional hysteresis band current controllers such as: high torque ripple, more current error, large variation in switching frequency etc. The proposed current controller is a hysteresis controller in which the hysteresis band is programmed as a function of variation of motor speed and load current. Any variation in those parameters causes an appropriate change in the band which in turns reduces the torque ripple as well as current error of the machine. The proposed scheme is modeled and tested in the MATLAB-Simulink environment for the effectiveness of the study. Further, the result is validated experimentally by using TMS320F2812 digital signal processor.

scholarly journals High-Speed and Unified ECC Processor for Generic Weierstrass Curves over GF(p) on FPGA

Sensors ◽  
2021 ◽  
Vol 21 (4) ◽  
pp. 1451
Author(s):  
Asep Muhamad Awaludin ◽  
Harashta Tatimma Larasati ◽  
Howon Kim
Keyword(s):  
Elliptic Curve ◽  
Digital Signal Processor ◽  
Execution Time ◽  
High Speed ◽  
Hardware Implementation ◽  
Digital Signal ◽  
Low Complexity ◽  
Montgomery Ladder ◽  
Modular Multiplier ◽  
Pipelined Multiplier

In this paper, we present a high-speed, unified elliptic curve cryptography (ECC) processor for arbitrary Weierstrass curves over GF(p), which to the best of our knowledge, outperforms other similar works in terms of execution time. Our approach employs the combination of the schoolbook long and Karatsuba multiplication algorithm for the elliptic curve point multiplication (ECPM) to achieve better parallelization while retaining low complexity. In the hardware implementation, the substantial gain in speed is also contributed by our n-bit pipelined Montgomery Modular Multiplier (pMMM), which is constructed from our n-bit pipelined multiplier-accumulators that utilizes digital signal processor (DSP) primitives as digit multipliers. Additionally, we also introduce our unified, pipelined modular adder/subtractor (pMAS) for the underlying field arithmetic, and leverage a more efficient yet compact scheduling of the Montgomery ladder algorithm. The implementation for 256-bit modulus size on the 7-series FPGA: Virtex-7, Kintex-7, and XC7Z020 yields 0.139, 0.138, and 0.206 ms of execution time, respectively. Furthermore, since our pMMM module is generic for any curve in Weierstrass form, we support multi-curve parameters, resulting in a unified ECC architecture. Lastly, our method also works in constant time, making it suitable for applications requiring high speed and SCA-resistant characteristics.

scholarly journals Real time emulator for parallel connected dual-PMSM sensorless control

2021 ◽  
Vol 12 (3) ◽  
pp. 1390
Author(s):  
Khaldoune Sahri ◽  
Maria Pietrzak-David ◽  
Lotfi Baghli ◽  
Abdelaziz Kheloui
Keyword(s):  
Real Time ◽  
Digital Signal Processor ◽  
Control Method ◽  
Permanent Magnet Synchronous Motor ◽  
Digital Signal ◽  
System Control ◽  
Actual System ◽  
Field Programmable ◽  
Physical Sensor ◽  
Xilinx Fpga

<p>This paper presents a real-time emulator of a dual permanent magnet synchronous motor (PMSM) drive implemented on a field-programmable gate array (FPGA) board for supervision and observation purposes. In order to increase the reliability of the drive, a sensorless speed control method is proposed. This method allows replacing the physical sensor while guaranteeing a satisfactory operation even in faulty conditions. The novelty of the proposed approach consists of an FPGA implementation of an emulator to control the actual system. Hence, this emulator operates in real-time with actual system control in healthy or faulty mode. It gives an observation of the speed rotation in case of fault for the sake of continuity of service. The observation of the rotor position and the speed are achieved using the dSPACE DS52030D digital platform with a digital signal processor (DSP) associated with a Xilinx FPGA.</p>

Sensorless Control of IPMSM Using Modified Current Slope Estimation Method

2012 ◽  
Vol 150 ◽  
pp. 100-104
Author(s):  
Tao Zhang ◽  
Wei Ni ◽  
Hui Ping Zhang ◽  
Sha Sha Wu
Keyword(s):  
Permanent Magnet ◽  
Digital Signal Processor ◽  
Permanent Magnet Synchronous Motor ◽  
Estimation Method ◽  
Digital Signal ◽  
Synchronous Motor ◽  
Low Speed ◽  
Rotor Position ◽  
Operating Region ◽  
Interior Permanent Magnet

When the permanent magnet synchronous motor is operated at a low speed. The rotor position and speed are very difficult to estimate using the extended flux or back EMF method. A novel modified current slope estimating method is used to estimate the rotor position and speed in low speed in this paper. The mathematical models of an interior permanent magnet synchronous motor (IPMSM) are deduced. The basic principle of modified current slope method is introduced. The simulation control system is built based on Matlab and a TMS320LF2407 digital signal processor is used to execute the rotor position and speed estimation. The experimental and simulation results have shown that the rotor position and speed can be accurately estimated in a low-speed operating region.

scholarly journals Argus CNN Accelerator Based on Kernel Clustering and Resource-Aware Pruning

2021 ◽  
Vol 27 (3) ◽  
pp. 57-70
Author(s):  
Damjan M. Rakanovic ◽  
Vuk Vranjkovic ◽  
Rastislav J. R. Struharik
Keyword(s):  
Digital Signal Processor ◽  
State Of The Art ◽  
Digital Signal ◽  
Pruning Algorithm ◽  
Kernel Clustering ◽  
Field Programmable ◽  
Comparable Performance ◽  
On Chip ◽  
Resource Characteristics ◽  
Resource Aware

Paper proposes a two-step Convolutional Neural Network (CNN) pruning algorithm and resource-efficient Field-programmable gate array (FPGA) CNN accelerator named “Argus”. The proposed CNN pruning algorithm first combines similar kernels into clusters, which are then pruned using the same regular pruning pattern. The pruning algorithm is carefully tailored for FPGAs, considering their resource characteristics. Regular sparsity results in high Multiply-accumulate (MAC) efficiency, reducing the amount of logic required to balance workloads among different MAC units. As a result, the Argus accelerator requires about 170 Look-up tables (LUTs) per Digital Signal Processor (DSP) block. This number is close to the average LUT/DPS ratio for various FPGA families, enabling balanced resource utilization when implementing Argus. Benchmarks conducted using Xilinx Zynq Ultrascale + Multi-Processor System-on-Chip (MPSoC) indicate that Argus is achieving up to 25 times higher frames per second than NullHop, 2 and 2.5 times higher than NEURAghe and Snowflake, respectively, and 2 times higher than NVDLA. Argus shows comparable performance to MIT’s Eyeriss v2 and Caffeine, requiring up to 3 times less memory bandwidth and utilizing 4 times fewer DSP blocks, respectively. Besides the absolute performance, Argus has at least 1.3 and 2 times better GOP/s/DSP and GOP/s/Block-RAM (BRAM) ratios, while being competitive in terms of GOP/s/LUT, compared to some of the state-of-the-art solutions.

scholarly journals Detection and control of a gyroscopically induced vibration to improve the balance of a single-wheel robot

2017 ◽  
Vol 37 (3) ◽  
pp. 443-455 ◽  
Author(s):  
Sangdeok Lee ◽  
Seul Jung
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Balance Control ◽  
A Priori ◽  
Experimental Studies ◽  
Notch Filter ◽  
Digital Signal ◽  
Control Performance ◽  
And Control ◽  
Balancing Control

In this article, an experimental investigation of the detection of a gyroscopically induced vibration and the balancing control performance of a single-wheel robot is presented. The balance of the single-wheel robot was intended to be maintained by virtue of the gyroscopic effect induced from a highly rotating flywheel. Since the flywheel rotates at a high speed, an asymmetrical structure of a flywheel causes an irregular rotation and becomes one of the major vibration sources. A vibration was detected and suppressed a priori before applying control algorithms to the robot. Gyroscopically induced vibrations can empirically be detected with different rotational velocities. The detection of the balancing angle of the single-wheel robot was accomplished by using an attitude and heading reference system. After identifying the vibrating frequencies, a notch filter was designed to suppress the vibration at the typical frequencies identified through experiments. A digital filter was designed and implemented in a digital signal processor(DSP) along with the control scheme for the balance control performance. The performance of the proposed method was verified by the experimental studies on the balancing control of the single-wheel robot. Experimental results confirmed that the notch filter designed following the detection of the flywheel’s vibration actually improved the balancing control performance. A half of the vibration magnitude was reduced by the proposal.

A Polarization Stabilization Control System Based on DSP

2014 ◽  
Vol 631-632 ◽  
pp. 806-810 ◽  
Author(s):  
Qing Xiang Hou ◽  
Xue Guang Yuan ◽  
Yan Gan Zhang ◽  
Jin Nan Zhang
Keyword(s):  
Control System ◽  
Digital Signal Processor ◽  
High Speed ◽  
Particle Swarm Optimization Algorithm ◽  
Low Frequency ◽  
Digital Signal ◽  
Rf Power ◽  
Swarm Optimization ◽  
Modified Particle Swarm Optimization ◽  
Stabilization Control

A polarization stabilization control system based on digital signal processor (DSP) is proposed in this paper. The system uses low frequency radio frequency (RF) power as control signal for polarization stabilization, and it does not need high-speed circuit to track fast polarization change. Modified particle swarm optimization algorithm is utilized and the effectiveness of polarization stabilization control is experimentally verified.

scholarly journals Decimation of Delta-Sigma-Modulated Signals Using a Low-Cost Microcontroller

2021 ◽  
Author(s):  
Markeljan Fishta ◽  
Franco Fiori
Keyword(s):  
Digital Signal Processor ◽  
High Speed ◽  
Low Cost ◽  
Digital Signal ◽  
Experimental Tests ◽  
General Purpose ◽  
Data Conversion ◽  
Clock Frequency ◽  
Main Challenge ◽  
Modulated Signals

Abstract$$\varDelta \varSigma $$ Δ Σ analog-to-digital converters (ADCs) are largely used in sensor acquisition applications. In the last few years, standalone $$\varDelta \varSigma $$ Δ Σ modulators have become increasingly available as off-the-shelf parts. To build a complete ADC, a standalone modulator has to be paired with some advanced elaboration unit, such as a field programmable gate array (FPGA) or a digital signal processor (DSP), which is needed for the implementation of the decimation filter. This work investigates the use of low-cost, general-purpose microcontrollers for the decimation of $$\varDelta \varSigma $$ Δ Σ -modulated signals. The main challenge is given by the clock frequency of the modulator, which can be in the range of a few $$\hbox {MHz}$$ MHz . The proposed technique deals with this limitation by employing two serial peripheral interface (SPI) modules in a time-interleaved configuration. This approach allows for continuous acquisition and elaboration of relatively high-speed, digital signals. The technique has been applied to a case study, and a data conversion system has been practically realized. The performance of the proposed filter is compared to that of a digital filter, present on board a commercial microcontroller, and the results of experimental tests are provided.

Low Power, High Speed and Area Efficient Binary Count Multiplier

2016 ◽  
Vol 25 (04) ◽  
pp. 1650027 ◽  
Author(s):  
Kore Sagar Dattatraya ◽  
Belgudri Ritesh Appasaheb ◽  
Ramdas Bhanudas Khaladkar ◽  
V. S. Kanchana Bhaaskaran
Keyword(s):  
Digital Signal Processor ◽  
Word Length ◽  
High Speed ◽  
Digital Signal ◽  
General Purpose ◽  
Computation Method ◽  
Partial Product ◽  
Wallace Tree ◽  
Power Delay Product ◽  
Binary Count

Multiplier forms the core building block of any processor, such as the digital signal processor (DSP) and a general purpose microprocessor. As the word length increases, the number of adders or compressors required for the partial product addition also increases. The addition operation of the derived partial products determines the circuit latency, area and speed performance of wider word-length multipliers. Binary count multiplier (BCM) aims to reduce the number of adders and compressors through the use of a uniquely structured binary counter and by suitably altering the logical flow of partial product addition by using binary adders is proposed in this paper. The binary counters for varying bit count values are derived by modifying the basic 4:2 compressor circuit. A [Formula: see text] bit multiplier has been developed to validate the proposed computation method. This logic structure demonstrates lower power operation, reduced device count and lesser delay in comparison against the conventional Wallace tree multiplier structure found in the literature. The BCM implementation realizes 29.17% reduction in the device count, 66% reduction in the delay and 70% reduction in the power dissipation. Furthermore, it realizes 90% reduction in the power delay product (PDP) in comparison against the Wallace tree structure. The multiplier circuits have been implemented and the validation of results has been carried out using Cadence[Formula: see text] EDA tool. Forty five nanometer technology files have been employed for the designs and exhaustive SPICE simulations.

Research of Permanent Magnet Synchronous Motor Speed Control System Based on DSP

2012 ◽  
Vol 468-471 ◽  
pp. 2891-2894 ◽  
Author(s):  
Hui Wang ◽  
Xue Ren Dong ◽  
Xiao Wei Yang ◽  
Feng Nan Liu
Keyword(s):  
Control System ◽  
Permanent Magnet ◽  
Digital Signal Processor ◽  
Permanent Magnet Synchronous Motor ◽  
Digital Signal ◽  
Speed Control ◽  
Synchronous Motor ◽  
Motor Speed ◽  
System Solution ◽  
Speed Control System

For requirements Permanent magnet synchronous motor (PMSM) speeds control, the digital signal processor (DSP) is used for speed control system of PMSM. By using space vector pulse width modulation (SVPWM) algorithm, system performance is improved, and system costs are reduced. In this paper, the principle of SVPWM is analyzed, and its implementation is described. Through the analysis of permanent magnet synchronous motor in a different coordinate system in the mathematical model system solution is presented, software design for system is described. A DSP-based PMSM speed control system is build, the system is analyzed in MATLAB simulation. That proves the feasibility of the system.

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