scholarly journals An Area-Efficient and Highly Linear Reconfigurable Continuous-Time Filter for Biomedical Sensor Applications

Sensors ◽  
2020 ◽  
Vol 20 (7) ◽  
pp. 2065 ◽  
Author(s):  
Jinyong Zhang ◽  
Shing-Chow Chan ◽  
Hui Li ◽  
Nannan Zhang ◽  
Lei Wang
Keyword(s):  
Continuous Time ◽  
Frequency Tuning ◽  
Cutoff Frequency ◽  
Harmonic Distortion ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Current Steering ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area

This paper proposes a compact, high-linearity, and reconfigurable continuous-time filter with a wide frequency-tuning capability for biopotential conditioning. It uses an active filter topology and a new operational-transconductance-amplifier (OTA)-based current-steering (CS) integrator. Consequently, a large time constant τ , good linearity, and linear bandwidth tuning could be achieved in the presented filter with a small silicon area. The proposed filter has a reconfigurable structure that can be operated as a low-pass filter (LPF) or a notch filter (NF) for different purposes. Based on the novel topology, the filter can be readily implemented monolithically and a prototype circuit was fabricated in the 0.18 μm standard complementary-metal–oxide–semiconductor (CMOS) process. It occupied a small area of 0.068 mm2 and consumed 25 μW from a 1.8 V supply. Measurement results show that the cutoff frequency of the LPF could be linearly tuned from 0.05 Hz to 300 Hz and the total-harmonic-distortion (THD) was less than −76 dB for a 2 Hz, 200 mVpp sine input. The input-referred noises were 5.5 μVrms and 6.4 μVrms for the LPF and NF, respectively. A comparison with conventional designs reveals that the proposed design achieved the lowest harmonic distortion and smallest on-chip capacitor. Moreover, its ultra-low cutoff frequency and relatively linear frequency tuning capability make it an attractive solution as an analog front-end for biopotential acquisitions.

The Design of Gm-C Low-Pass Filter for Micromachined Gyroscope

2014 ◽  
Vol 609-610 ◽  
pp. 1072-1076
Author(s):  
Qiu Ye Lv ◽  
Chong He ◽  
Wen Jie Fan ◽  
Yu Feng Zhang ◽  
Xiao Wei Liu
Keyword(s):  
Process Model ◽  
Stop Band ◽  
Cutoff Frequency ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
Simulation Results ◽  
Micromachined Gyroscope

In this Paper, a 4th-Order Low-Pass Gm-C Filter is Presented. for the Design of Operational Tranconductance Amplifier(OTA), it Adopts the Techniques of Current Division and Current Cancellation. these Techniques can Help to Achieve a Low Transconductance Value. for the Architecture of the 4th-Order Gm-C Filter, it Consists of Two Biquads. the Two Biquads are Cascade Connected. the Gm-C Low-Pass Filter has been Implemented under 0.5 μm CMOS Process Model. the Final Simulation Results Show the Cutoff Frequency of the Filter is 100Hz and the Stop-Band Attenuation is Larger than 60dB. the Power Consumption is Lower than 1mW and the Total Harmonic Distortion(THD) is -55dB.

scholarly journals A Two-Module Linear Regulator with 3.9–10 V Input, 2.5 V Output, and 500 mA Load

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1143
Author(s):  
Quanzhen Duan ◽  
Weidong Li ◽  
Shengming Huang ◽  
Yuemin Ding ◽  
Zhen Meng ◽  
...  
Keyword(s):  
Complementary Metal Oxide Semiconductor ◽  
Input Voltage ◽  
Low Noise ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area ◽  
Chip Area ◽  
Linear Regulator

A linear regulator with an input range of 3.9–10 V, 2.5 V output, and a maximal 500 mA load for use with battery systems was developed and presented here. The linear regulator featured two modules of a preregulator and a linear regulator core circuit, offering minimized power dissipation and high-level stability. The preregulator delivered an internal power voltage of 3 V and supplied internal circuits including the second module (the linear regulator core). The preregulator fitted with an active, low-pass filter provided a low-noise reference voltage to the linear regulator core circuit. To ensure operational stability for the linear regulator, error amplifiers incorporating the Miller compensation technique and featuring a large slewing rate were employed in the two modules. The circuit was successfully implemented in a 0.25 µm, 5 V complementary metal-oxide semiconductor (CMOS) process featuring 20 V drain-extended MOS (DMOS)/bipolar high-voltage devices. The total silicon area, including all pads, was approximately 1.67 mm2. To reduce chip area, bipolar rather than DMOS transistors served as the power transistors. Measured results demonstrated that the designed linear regulator was able to operate at an input voltage ranging from 3.9 to 10 V and offer a maximum 500 mA load current with fixed 2.5 V output voltage.

scholarly journals Wideband Reconfigurable Integrated Low-Pass Filter for 5G Compatible Software Defined Radio Solutions

Electronics ◽  
2021 ◽  
Vol 10 (6) ◽  
pp. 734
Author(s):  
Karolis Kiela ◽  
Marijan Jurgo ◽  
Vytautas Macaitis ◽  
Romualdas Navickas
Keyword(s):  
Software Defined Radio ◽  
Dynamic Range ◽  
Noise Figure ◽  
Harmonic Distortion ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Filter Performance ◽  
Low Pass ◽  
Bandwidth Tuning

This article presents a wideband reconfigurable integrated low-pass filter (LPF) for 5G NR compatible software-defined radio (SDR) solutions. The filter uses Active-RC topology to achieve high linearity performance. Its bandwidth can be tuned from 2.5 MHz to 200 MHz, which corresponds to a tuning ratio of 92.8. The order of the filter can be changed between the 2nd, 4th, or 6th order; it has built-in process, voltage, and temperature (PVT) compensation with a tuning range of ±42%; and power management features for optimization of the filter performance across its entire range of bandwidth tuning. Across its entire order, bandwidth, and power configuration range, the filter achieves in-band input-referred third-order intercept point (IIP3) between 32.7 dBm and 45.8 dBm, spurious free dynamic range (SFDR) between 63.6 dB and 79.5 dB, 1 dB compression point (P1dB) between 9.9 dBm and 14.1 dBm, total harmonic distortion (THD) between −85.6 dB and −64.5 dB, noise figure (NF) between 25.9 dB and 31.8 dB and power dissipation between 1.19 mW and 73.4 mW. The LPF was designed and verified using 65 nm CMOS process; it occupies a 0.429 mm2 area of silicon and uses a 1.2 V supply.

Design and Simulation of Switched Capacitor Filter for Speed Change Parameter Converter

2013 ◽  
Vol 562-565 ◽  
pp. 1132-1136
Author(s):  
Xiao Wei Liu ◽  
Jian Yang ◽  
Song Chen ◽  
Liang Liu ◽  
Rui Zhang ◽  
...  
Keyword(s):  
Stop Band ◽  
Cutoff Frequency ◽  
Rapid Change ◽  
Pass Band ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Low Pass ◽  
The Time Domain

In this paper, we design a high-order switched capacitor filter for rapid change parameter converter. This design uses a structure which consists of three biquads filter sub-units. The design is a 6th-order SC elliptic low-pass filter, and the sample frequency is 250 kHz. By the MATLAB Simulink simulation, the system can meet the design requirements in the time domain. In this paper, the 6th-order switched capacitor elliptic low-pass filter was implemented under 0.5 um CMOS process and simulated in Cadence. The final simulation results show that the pass-band cutoff frequency is 10 kHz, and the maximum pass-band ripple is about 0.106 dB. The stop-band cutoff frequency is 20 kHz, and the minimum stop-band attenuation is 74.78 dB.

scholarly journals A CMOS Low Pass Filter for SoC Lock-in-Based Measurement Devices

Sensors ◽  
2019 ◽  
Vol 19 (23) ◽  
pp. 5173 ◽  
Author(s):  
Jorge Pérez-Bailón ◽  
Belén Calvo ◽  
Nicolás Medrano
Keyword(s):  
Dynamic Range ◽  
Current Trend ◽  
Cutoff Frequency ◽  
Oxide Semiconductor ◽  
Constant Current ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Compact Size ◽  
Low Pass ◽  
Lock In

This paper presents a fully integrated Gm–C low pass filter (LPF) based on a current steering Gm reduction-tuning technique, specifically designed to operate as the output stage of a SoC lock-in amplifier. To validate this proposal, a first-order and a second-order single-ended topology were integrated into a 1.8 V to 0.18 µm CMOS (Complementary Metal-Oxide-Semiconductor) process, showing experimentally a tuneable cutoff frequency that spanned five orders of magnitude, from tens of mHz to kHz, with a constant current consumption (below 3 µA/pole), compact size (<0.0140 mm2/pole), and a dynamic range better than 70 dB. Compared to state-of-the-art solutions, the proposed approach exhibited very competitive performances while simultaneously fully satisfying the demanding requirements of on-chip portable measurement systems in terms of highly efficient area and power. This is of special relevance, taking into account the current trend towards multichannel instruments to process sensor arrays, as the total area and power consumption will be proportional to the number of channels.

scholarly journals A CMOS Programmable Fourth-Order Butterworth Active-RC Low-Pass Filter

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 204 ◽  
Author(s):  
Changchun Zhang ◽  
Long Shang ◽  
Yongkai Wang ◽  
Lu Tang
Keyword(s):  
Radio Frequency Identification ◽  
Supply Voltage ◽  
Cutoff Frequency ◽  
Cmos Technology ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area ◽  
Fully Differential ◽  
Low Pass ◽  
Low Sensitivity

This paper presents a low-pass filter (LPF) for an ultra-high frequency (UHF) radio frequency identification (RFID) reader transmitter in standard SMIC 0.18 μm CMOS technology. The active-RC topology and Butterworth approximation function are employed mainly for high linearity and high flatness respectively. Two cascaded fully-differential Tow-Thomas biquads are chosen for low sensitivity to process errors and strong resistance to the imperfection of the involved two-stage fully-differential operational amplifiers. Besides, the LPF is programmable in order to adapt to the multiple data rate standards. Measurement results show that the LPF has the programmable bandwidths of 605/870/1020/1330/1530/2150 kHz, the optimum input 1dB compression point of −7.81 dBm, and the attenuation of 50 dB at 10 times cutoff frequency, with the overall power consumption of 12.6 mW from a single supply voltage of 1.8 V. The silicon area of the LPF core is 0.17 mm2.

LOW-POWER, LOW-VOLTAGE, DUAL-OUTPUT, SECOND GENERATION CURRENT CONVEYOR AND ITS APPLICATION IN LOW-PASS FILTER DESIGN

2013 ◽  
Vol 22 (06) ◽  
pp. 1350044 ◽  
Author(s):  
MOHAMMAD HOSSEIN MAGHAMI ◽  
AMIR M. SODAGAR
Keyword(s):  
Second Generation ◽  
Current Conveyor ◽  
The Body ◽  
Total Power ◽  
Cmos Process ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Silicon Area ◽  
Total Power Consumption ◽  
Low Pass

A new simple dual-output second generation current conveyor (DO-CCII) circuit is proposed. Designed in a standard 0.5-μm CMOS process, the circuit operates at ±1.5 V supply voltages with a total power consumption of 106 nW. Main characteristics of the proposed DO-CCII are its simplicity, small silicon area consumption, and not suffering from the body effect of MOS transistors. The proposed circuit is employed to implement a first-order low-pass filter with upper -3 dB cut-off frequency of as low as 3.2 Hz.

scholarly journals 0.5 V Fifth-Order Butterworth Low-Pass Filter Using Multiple-Input OTA for ECG Applications

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7343
Author(s):  
Montree Kumngern ◽  
Nattharinee Aupithak ◽  
Fabian Khateb ◽  
Tomasz Kulej
Keyword(s):  
Power Consumption ◽  
Dynamic Range ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Subthreshold Region ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Multiple Input ◽  
Low Pass ◽  
Fifth Order

This paper presents a 0.5 V fifth-order Butterworth low-pass filter based on multiple-input operational transconductance amplifiers (OTA). The filter is designed for electrocardiogram (ECG) acquisition systems and operates in the subthreshold region with nano-watt power consumption. The used multiple-input technique simplifies the overall structure of the OTA and reduces the number of active elements needed to realize the filter. The filter was designed and simulated in the Cadence environment using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process from Taiwan Semiconductor Manufacturing Company (TSMC). Simulation results show that the filter has a bandwidth of 250 Hz, a power consumption of 34.65 nW, a dynamic range of 63.24 dB, attaining a figure-of-merit of 0.0191 pJ. The corner (process, voltage, temperature: PVT) and Monte Carlo (MC) analyses are included to prove the robustness of the filter.

A CMOS Fourth-Order 150Hz Low-Pass Filter for Sensor Applications

2013 ◽  
Vol 380-384 ◽  
pp. 3320-3323
Author(s):  
Chang Chun Dong ◽  
Nan Nan Liu ◽  
Zhan Peng Jiang
Keyword(s):  
Fourth Order ◽  
Cutoff Frequency ◽  
Cmos Process ◽  
Sensor Interface ◽  
Pass Filter ◽  
Low Pass Filter ◽  
Sensor Applications ◽  
Low Pass ◽  
Cascade Structure ◽  
Simulation Results

A low-pass filter for the sensor is presented, which based on the linearized transconductance structure and the capacitance scaler schemes. The filter adopt fourth order cascade structure, and simulation by 0.5μm CMOS process. Simulation results for the filter show a cutoff frequency of 150Hz, while band ripple is less than 0.8 dB. The power consumption for the filter is only 1.6mW, meet the requirements of the sensor interface ASIC for low-pass filter.

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