scholarly journals Digital Circuit for Seamless Resampling ADC Output Streams

Sensors ◽  
2020 ◽  
Vol 20 (6) ◽  
pp. 1619 ◽  
Author(s):  
Mauro D’Arco ◽  
Ettore Napoli ◽  
Efstratios Zacharelos
Keyword(s):  
Integrated Circuit ◽  
Memory Management ◽  
Sampling Rate ◽  
Digital Signal ◽  
Digital Circuit ◽  
Clock Frequency ◽  
Storage Oscilloscope ◽  
Analog To Digital ◽  
Digital Storage ◽  
Fine Resolution

Fine resolution selection of the sample rate is not available in digital storage oscilloscopes (DSOs), so the user has to rely on offline processing to cope with such need. The paper first discusses digital signal processing based methods that allow changing the sampling rate by means of digital resampling approaches. Then, it proposes a digital circuit that, if included in the acquisition channel of a digital storage oscilloscope, between the internal analog-to-digital converter (ADC) and the acquisition memory, allows the user to select any sampling rate lower than the maximum one with fine resolution. The circuit relies both on the use of a short digital filter with dynamically generated coefficients and on a suitable memory management strategy. The output samples produced by the digital circuit are characterized by a sampling rate that can be incoherent with the clock frequency regulating the memory access. Both a field programmable gate array (FPGA) implementation and an application specific integrated circuit (ASIC) design of the proposed circuit are evaluated.

scholarly journals Information Entropy- and Average-Based High-Resolution Digital Storage Oscilloscope

2014 ◽  
Vol 2014 ◽  
pp. 1-12 ◽  
Author(s):  
Jun Jiang ◽  
Lianping Guo ◽  
Kuojun Yang ◽  
Huiqing Pan
Keyword(s):  
Data Fusion ◽  
Information Entropy ◽  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Storage Oscilloscope ◽  
Whole Process ◽  
Digital Storage ◽  
Gross Error ◽  
Digital Storage Oscilloscope ◽  
Sample Data

Vertical resolution is an essential indicator of digital storage oscilloscope (DSO) and the key to improving resolution is to increase digitalizing bits and lower noise. Averaging is a typical method to improve signal to noise ratio (SNR) and the effective number of bits (ENOB). The existing averaging algorithm is apt to be restricted by the repetitiveness of signal and be influenced by gross error in quantization, and therefore its effect on restricting noise and improving resolution is limited. An information entropy-based data fusion and average-based decimation filtering algorithm, proceeding from improving average algorithm and in combination with relevant theories of information entropy, are proposed in this paper to improve the resolution of oscilloscope. For single acquiring signal, resolution is improved through eliminating gross error in quantization by utilizing the maximum entropy of sample data with further noise filtering via average-based decimation after data fusion of efficient sample data under the premise of oversampling. No subjective assumptions and constraints are added to the signal under test in the whole process without any impact on the analog bandwidth of oscilloscope under actual sampling rate.

Delta-Sigma Digital-to-Time Converter for Band-Select Spread Spectrum Clock

2015 ◽  
Vol 643 ◽  
pp. 79-91 ◽  
Author(s):  
Ramin Khatami ◽  
Haruo Kobayashi ◽  
Yasunori Kobori
Keyword(s):  
Spread Spectrum ◽  
Digital Signal ◽  
Noise Spectrum ◽  
Digital Circuit ◽  
Clock Frequency ◽  
Clock Generation ◽  
Delta Sigma ◽  
Fm Radio ◽  
Modulation Methods ◽  
Spectrum Spread

This paper proposes an innovative method of converting digital signal to time-domain analog signal, which fully enjoys robustness and digital circuit friendliness. This technique utilizes a digital delta-sigma ( ) modulator following a digital-to-time converter (DTC) circuit with various modulation methods. As an application of the proposed method, novel spreadspectrum clock generation (SSCG) algorithms (such as for DC-DC converters) have been investigated which can select the noise spectrum spread bands; e.g., they can exclude the noisespectrum spread in AM, FM radio bands. The proposed circuit takes advantage of digital technology, which is simple, fast (reachable at high clock frequency) and flexible (programmable).

A TIME-DOMAIN 1.0-V/0.8-MW 6-BIT 125 MS/S FLASH ADC IN 65 NM CMOS

2013 ◽  
Vol 22 (04) ◽  
pp. 1350017 ◽  
Author(s):  
GUANZHONG HUANG ◽  
PINGFEN LIN
Keyword(s):  
Time Domain ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Sampling Rate ◽  
Digital Signal ◽  
Input Voltage ◽  
Gray Code ◽  
Digital Circuit ◽  
Cmos Process ◽  
Flash Adc

A 6-bit low-voltage power-efficient flash analog-to-digital converter (ADC) is presented in this paper. The proposed ADC replaces the conventional voltage comparator with a new approach in the time-domain. The reference voltages and the analog input voltage are converted to digital signal in a form of different pulse widths by using a pulse-width-modulation (PWM) circuit. Consequently, the comparison is achieved by checking the sequence of the pulse rising edges rather than amplifying and latching the voltage difference. The total input capacitance of the proposed ADC is as small as tens of femto-farads, resulting in much less demand for the front-end buffer and the sampling switch. In addition, an implementation of the digital foreground calibration helps to get rid of the nonmonotonic comparison thresholds due to mismatch. The calibration operates with the adaptive comparison threshold by tuning the modulation level of the PWM. The intermediate Gray code conversion increases the bubble tolerance by 1LSB. This digital-circuit-heavily-involved ADC has been designed and simulated in a 65 nm CMOS process, achieving 35.24 dB signal-to-noise-and-distortion-ratio (SNDR) at a sampling rate of 125 MS/s while consuming 803 μW from 1 V power supply. As a result, the figure of merit (FoM) is as low as 136 fJ/conversion-step.

Low Power High Performance Full Adder Design Using Gate Diffusion Input Techniques

2020 ◽  
Vol 17 (4) ◽  
pp. 1595-1599
Author(s):  
N. Suresh ◽  
K. Subba Rao ◽  
R. Vassoudevan
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Integrated Circuit ◽  
High Performance ◽  
Large Scale ◽  
Digital Signal ◽  
Full Adder ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Essential Components

Very Large Scale Integrated (VLSI) technology for a widespread use of high performance portable integrated circuit (IC) devices such as MP3, PDA, mobile phones is increasing rapidly. Most of the VLSI applications, such as digital signal processing, image processing and microprocessors, extensively use arithmetic operations. In this research novel low power full adder architecture has been proposed for various applications which uses the advanced adder and multiplier designs. A full-adder is one of the essential components in digital circuit design; many improvements have been made to reduce the architecture of a full adder. In this research modified full adder using GDI technique is proposed to achieve low power consumption. By using GDI cell, the transistor count is greatly reduced, thereby reducing the power consumption and propagation delay while maintaining the low complexity of the logic design. The parameters in terms of Power, Delay, and Surface area are investigated by comparison of the proposed GDI technology with an optimized 90 nm CMOS technology.

Field-Programmable Gate Array-Based Hardware Design of Optical Fiber Transducer Integrated Platform

2020 ◽  
Vol 15 (5) ◽  
pp. 663-671
Author(s):  
Kai-Chun Chu ◽  
Kuo-Chi Chang ◽  
Hsiao-Chuan Wang ◽  
Yuh-Chung Lin ◽  
Tsui-Lien Hsu
Keyword(s):  
Raman Scattering ◽  
Optical Fiber ◽  
Integrated Circuit ◽  
Sampling Rate ◽  
Nand Flash ◽  
Control Logic ◽  
Analog To Digital ◽  
Integrated Platform ◽  
Field Programmable ◽  
Distributed Optical Fiber

This study focuses on the hardware architecture of a Raman scattering distributed optical fiber transducer platform, the principles of Raman scattering are analyzed, and the output 2 analog electrical signals are converted to digital signals at a 16-bit sampling rate by an Analog-to-Digital Converter (ADC). The system is implemented based on the FPGA. The integrated circuit is responsible for controlling the data acquisition process. The differential amplifier circuit, FPGA peripheral circuit, and CPU subsystem circuit, which takes ARM as the core, are separately designed. The composition of software includes a DDR2 (Double Data Rate 2) driver and central control logic. In this study, the optical fiber transducer platform has been tested. The CPU DDR2 is read/written by the test program respectively. According to the results, the program passes the read/write test. The NAND FLASH is tested. The results show that this program returns all operations successfully. The timing tests of the DDR2 interface and data latching are conducted. The results show that the read/write operations ensure that the clock and data curves are aligned. Therefore, the optical fiber transducer integrated platform designed in this study is effective.

scholarly journals Research and Development on an Embedded Digital Storage Oscilloscope Based on PXA 270

2018 ◽  
Vol 2 (2) ◽  
pp. 44
Author(s):  
Pengyun Zhang ◽  
Guonan Feng ◽  
Zhiqiang He
Keyword(s):  
Sampling Rate ◽  
Embedded Software ◽  
Time Sampling ◽  
Development Environment ◽  
Storage Oscilloscope ◽  
Digital Storage ◽  
Digital Storage Oscilloscope ◽  
Design Requirements ◽  
And Control ◽  
Actual Test

Abstract: This paper discusses the chief techniques and design principles of an embedded digital storage oscilloscope based on PXA 270, using FPGA as logic controller cell. The data acquisition partition consists of pre-process circuit, A/D converter, on-board memories, and control circuit integrated in FPGA. In the PB and EVC development environment, developers realized the part of embedded software. Actual test showed that the highest real-time sampling rate of the oscilloscope is up to 1GHz/s, which has achieved the desired design requirements.

scholarly journals The SALT—Readout ASIC for Silicon Strip Sensors of Upstream Tracker in the Upgraded LHCb Experiment

Sensors ◽  
2021 ◽  
Vol 22 (1) ◽  
pp. 107
Author(s):  
Carlos Abellan Abellan Beteta ◽  
Dimitra Andreou ◽  
Marina Artuso ◽  
Andy Beiter ◽  
Steven Blusk ◽  
...  
Keyword(s):  
Integrated Circuit ◽  
Pulse Shaping ◽  
Signal To Noise Ratio ◽  
Hadron Collider ◽  
Silicon Detector ◽  
Digital Signal ◽  
Analog To Digital ◽  
Lhcb Experiment ◽  
Application Specific Integrated Circuit ◽  
Application Specific

SALT, a new dedicated readout Application Specific Integrated Circuit (ASIC) for the Upstream Tracker, a new silicon detector in the Large Hadron Collider beauty (LHCb) experiment, has been designed and developed. It is a 128-channel chip using an innovative architecture comprising a low-power analogue front-end with fast pulse shaping and a 40 MSps 6-bit Analog-to-Digital Converter (ADC) in each channel, followed by a Digital Signal Processing (DSP) block performing pedestal and Mean Common Mode (MCM) subtraction and zero suppression. The prototypes of SALT were fabricated and tested, confirming the full chip functionality and fulfilling the specifications. A signal-to-noise ratio of about 20 is achieved for a silicon sensor with a 12 pF input capacitance. In this paper, the SALT architecture and measurements of the chip performance are presented.

scholarly journals Different Analog to Digital Converters Architectures

2020 ◽  
Vol 9 (4) ◽  
pp. 1256-1263
Keyword(s):  
Signal To Noise Ratio ◽  
Sampling Rate ◽  
Digital Signal ◽  
Vital Role ◽  
Analog To Digital Converters ◽  
Signal To Noise ◽  
Analog To Digital ◽  
Differential Nonlinearity ◽  
Gain Error ◽  
The Comparative Study

A series of recent studies has indicated that a mixed signal device analog to digital converters used for the processing of information and play a vital role in wireless sensors, Digital signal processing, Biomedical devices, in communication, IOT and various other applications. Across this broad use they give the significance in designing. The paper represents the various parameters like speed, area occupied, power consumption, sampling Rate, precision, Signal to noise ratio, Signal to noise distortion ratio, resolution, linearity and conversion time with respect to its different types and broad application in the real world. It defines errors due to non – linearity of signals as Differential nonlinearity, Integral nonlinearity, gain error, quantization error, aliasing and offset error. It also gives the comparative study about ADCs.

Timing Skew Calibration Method for TIADC-Based 20 GSPS Digital Storage Oscilloscope

2015 ◽  
Vol 25 (02) ◽  
pp. 1650007 ◽  
Author(s):  
Kuojun Yang ◽  
Jiali Shi ◽  
Shulin Tian ◽  
Wuhuang Huang ◽  
Peng Ye
Keyword(s):  
Input Signal ◽  
Sampling Rate ◽  
Calibration Method ◽  
Signal Frequency ◽  
Accurate Estimation ◽  
Storage Oscilloscope ◽  
Digital Storage ◽  
Digital Storage Oscilloscope ◽  
Time Interleaved ◽  
Timing Skew

Time-interleaved technique is widely used to increase the sampling rate of analog-to-digital converter (ADC). However, the channel mismatches degrade the performance of time-interleaved ADC (TIADC). When input signal frequency is very high, timing skews have significant effect on distortion. Therefore, a new timing skew calibration method is proposed in this paper. This method is based on the truth that timing skews are related to the product of the outputs of sub-ADCs. After timing skews are estimated, the digital controlled delay elements (DCDE) in ADC and phase locked loop (PLL) are utilized to calibrate timing skews. No auxiliary circuit and digital filter are needed for this calibration method. Simulation results show that the proposed method can estimate timing skew accurately. It is also proved that an accurate estimation can be obtained even the signal to noise ratio (SNR) of input signal is 20[Formula: see text]dB. The proposed method is employed to calibrate timing skews in a 16-channel TIADC-based 20[Formula: see text]GSPS digital storage oscilloscope (DSO). The experiment results demonstrate the usefulness of the proposed method. We can see that after timing skews are calibrated, the spectrum spurs have been effectively eliminated.

ВЫСОКОТЕМПЕРАТУРНЫЙ ДЕЛЬТА-СИГМА-АЦП

2020 ◽  
Vol 96 (3s) ◽  
pp. 182-186
Author(s):  
А.С. Коротков ◽  
Д.В. Морозов ◽  
М.М. Пилипко ◽  
М.С. Енученко
Keyword(s):  
Integrated Circuit ◽  
Supply Voltage ◽  
Operating Temperature ◽  
Silicon On Insulator ◽  
Digital Converter ◽  
Clock Frequency ◽  
Analog To Digital ◽  
Delta Sigma ◽  
Working Frequency ◽  
Silicon On Insulator Technology

Представлены результаты разработки специализированной интегральной схемы 12-разрядного дельта-сигма-АЦП с тактовой частотой 5 МГц и полосой рабочих частот 50 кГц при напряжении питания 3,3 В и рабочей температуре до 175 градусов Цельсия. Кристалл интегральной схемы изготовлен по программе «Европрактика» по технологии компании X-FAB XT018 «кремний на изоляторе» и используется в сенсорной сети для мониторинга состояния высокотемпературных объектов. The paper presents the development results of a specialized integrated circuit of a twelve-bit delta-sigma analog-to-digital converter with a clock frequency of 5 MHz and a working frequency band of 50 kHz with a supply voltage of 3.3 V and an operating temperature of up to 175 degrees Celsius. The integrated circuit die was manufactured within “Europractice” program using the X-FAB XT018 silicon-on-insulator technology and is used in the sensor network to monitor the state of high-temperature objects.

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