Field-Programmable Gate Array-Based Hardware Design of Optical Fiber Transducer Integrated Platform

2020 ◽  
Vol 15 (5) ◽  
pp. 663-671
Author(s):  
Kai-Chun Chu ◽  
Kuo-Chi Chang ◽  
Hsiao-Chuan Wang ◽  
Yuh-Chung Lin ◽  
Tsui-Lien Hsu
Keyword(s):  
Raman Scattering ◽  
Optical Fiber ◽  
Integrated Circuit ◽  
Sampling Rate ◽  
Nand Flash ◽  
Control Logic ◽  
Analog To Digital ◽  
Integrated Platform ◽  
Field Programmable ◽  
Distributed Optical Fiber

This study focuses on the hardware architecture of a Raman scattering distributed optical fiber transducer platform, the principles of Raman scattering are analyzed, and the output 2 analog electrical signals are converted to digital signals at a 16-bit sampling rate by an Analog-to-Digital Converter (ADC). The system is implemented based on the FPGA. The integrated circuit is responsible for controlling the data acquisition process. The differential amplifier circuit, FPGA peripheral circuit, and CPU subsystem circuit, which takes ARM as the core, are separately designed. The composition of software includes a DDR2 (Double Data Rate 2) driver and central control logic. In this study, the optical fiber transducer platform has been tested. The CPU DDR2 is read/written by the test program respectively. According to the results, the program passes the read/write test. The NAND FLASH is tested. The results show that this program returns all operations successfully. The timing tests of the DDR2 interface and data latching are conducted. The results show that the read/write operations ensure that the clock and data curves are aligned. Therefore, the optical fiber transducer integrated platform designed in this study is effective.

scholarly journals SYNTHESIS AND FPGA–IMPLEMENTATION BASED NEURAL TECHNIQUE OF A NONLINEAR ADC MODEL

2014 ◽  
pp. 27-33
Author(s):  
Mounir Bouhedda ◽  
Mokhtar Attari
Keyword(s):  
Integrated Circuit ◽  
Field Programmable Gate Array ◽  
High Speed ◽  
Hardware Description Language ◽  
Description Language ◽  
Analog To Digital ◽  
Field Programmable ◽  
Hardware Description ◽  
Nonlinear Analog ◽  
Very High

The aim of this paper is to introduce a new architecture using Artificial Neural Networks (ANN) in designing a 6-bit nonlinear Analog to Digital Converter (ADC). A study was conducted to synthesise an optimal ANN in view to FPGA (Field Programmable Gate Array) implementation using Very High-speed Integrated Circuit Hardware Description Language (VHDL). Simulation and tests results are carried out to show the efficiency of the designed ANN.

scholarly journals A Single-Amplifier Dual-Residue Pipelined-SAR ADC

Electronics ◽  
2021 ◽  
Vol 10 (4) ◽  
pp. 421
Author(s):  
Min-Jae Seo
Keyword(s):  
Dynamic Range ◽  
Sampling Rate ◽  
Cmos Technology ◽  
Open Loop ◽  
Sar Adc ◽  
Total Power ◽  
Control Logic ◽  
Analog To Digital ◽  
The One ◽  
And Control

This work presents a 12 bit 200 MS/s dual-residue pipelined successive approximation registers (SAR) analog-to-digital converter (ADC) with a single open-loop residue amplifier (RA). By using the inherent characteristics of the SAR conversion scheme, the proposed ADC sequentially generates two residue levels from the single RA, which eliminates the need for inter-stage gain-matching calibration. To convert the sequentially generated the two residues, a capacitive interpolating SAR ADC (I-SAR ADC) is also proposed. The I-SAR ADC is very compact because it consists of the one comparator, a CDAC, and control logic like a conventional SAR ADC. In addition, the I-SAR ADC needs no static power dissipation for the residue interpolation. A prototype ADC fabricated in a 40 nm CMOS technology occupies an active area of 0.026 mm2. At a 200 MS/s sampling-rate with the Nyquist input, the ADC achieves an SNDR (Signal-to-Noise distortion ratio) of 62.1 dB and 67.1 dB SFDR (Spurious-Free Dynamic Range), respectively. The total power consumed is 3.9 mW under a 0.9 V supply. Without any inter-stage mismatch calibration, the ADC achieve Walden Figure-of-Merit (FoM) of 19.0 fJ/conversion-step.

scholarly journals Digital Circuit for Seamless Resampling ADC Output Streams

Sensors ◽  
2020 ◽  
Vol 20 (6) ◽  
pp. 1619 ◽  
Author(s):  
Mauro D’Arco ◽  
Ettore Napoli ◽  
Efstratios Zacharelos
Keyword(s):  
Integrated Circuit ◽  
Memory Management ◽  
Sampling Rate ◽  
Digital Signal ◽  
Digital Circuit ◽  
Clock Frequency ◽  
Storage Oscilloscope ◽  
Analog To Digital ◽  
Digital Storage ◽  
Fine Resolution

Fine resolution selection of the sample rate is not available in digital storage oscilloscopes (DSOs), so the user has to rely on offline processing to cope with such need. The paper first discusses digital signal processing based methods that allow changing the sampling rate by means of digital resampling approaches. Then, it proposes a digital circuit that, if included in the acquisition channel of a digital storage oscilloscope, between the internal analog-to-digital converter (ADC) and the acquisition memory, allows the user to select any sampling rate lower than the maximum one with fine resolution. The circuit relies both on the use of a short digital filter with dynamically generated coefficients and on a suitable memory management strategy. The output samples produced by the digital circuit are characterized by a sampling rate that can be incoherent with the clock frequency regulating the memory access. Both a field programmable gate array (FPGA) implementation and an application specific integrated circuit (ASIC) design of the proposed circuit are evaluated.

Temperature Calibration of Distributed Optical Fiber Temperature Sensor Based on Raman Scattering

2015 ◽  
Vol 44 (5) ◽  
pp. 506006 ◽  
Author(s):  
汤玉泉 TANG Yu-quan ◽  
孙苗 SUN Miao ◽  
李俊 LI Jun ◽  
杨爽 YANG Shuang ◽  
Brian Culshaw Brian Culshaw ◽  
...  
Keyword(s):  
Raman Scattering ◽  
Optical Fiber ◽  
Temperature Sensor ◽  
Temperature Calibration ◽  
Distributed Optical Fiber

scholarly journals Distributed optical fiber temperature sensor using only anti-Stokes Raman scattering light in a loop configuration

2011 ◽  
Author(s):  
Marcelo A. Soto ◽  
Alessandro Signorini ◽  
Tiziano Nannipieri ◽  
Stefano Faralli ◽  
Gabriele Bolognini ◽  
...  
Keyword(s):  
Raman Scattering ◽  
Optical Fiber ◽  
Temperature Sensor ◽  
Scattering Light ◽  
Distributed Optical Fiber ◽  
Anti Stokes

Segment Compressive Sensing of Pipeline Data by Sequential Approach

2014 ◽  
Vol 513-517 ◽  
pp. 2787-2790
Author(s):  
Hong Jie Wan ◽  
Jing Ma ◽  
Wei Guo Lin ◽  
Bo Ran Yu
Keyword(s):  
Optical Fiber ◽  
Compressive Sensing ◽  
Sampling Rate ◽  
Warning System ◽  
Experimental Results ◽  
Signal Recovery ◽  
Sequential Approach ◽  
Event Location ◽  
Distributed Optical Fiber ◽  
Very High

In distributed optical fiber pipeline pre-warning system, the sampling rate is very high for threatening event location, so vast data will be generated which is inconvenient for transfer or storage. This paper adopts the compressive sensing approach to reduce the data quantity. The sparsity of each segment of the signal is important for signal recovery, and it controls the measurement number needed. However, the sparsity of every segment is difficult to achieve. In this paper, the sequential approach is used to fix the measurement number of each segment of the optical fiber pipeline data. This segment sequential approach further reduces the amount of data on the basis of compressive sensing. Simulation is carried out on the actual optical fiber pipeline pre-warning data, and the experimental results show that the reconstruction SNR could exceed 26dB using this algorithm.

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