scholarly journals Preparation of Polyimide/Graphene Oxide Nanocomposite and Its Application to Nonvolatile Resistive Memory Device

Polymers ◽  
2018 ◽  
Vol 10 (8) ◽  
pp. 901 ◽  
Author(s):  
Ju-Young Choi ◽  
Hwan-Chul Yu ◽  
Jeongjun Lee ◽  
Jihyun Jeon ◽  
Jaehyuk Im ◽  
...  

2,6-Diaminoanthracene (AnDA)-functionalized graphene oxide (GO) (AnDA-GO) was prepared and used to synthesize a graphene oxide-based polyimide (PI-GO) by the in-situ polymerization method. A PI-GO nanocomposite thin film was prepared and characterized by infrared (IR) spectroscopy, thermogravimetric analysis (TGA) and UV-visible spectroscopy. The PI-GO film was used as a memory layer in the fabrication of a resistive random access memory (RRAM) device with aluminum (Al) top and indium tin oxide (ITO) bottom electrodes. The device showed write-once-read-many-times (WORM) characteristics with a high ON/OFF current ratio (Ion/Ioff = 3.41 × 108). This excellent current ratio was attributed to the high charge trapping ability of GO. In addition, the device had good endurance until the 100th cycle. These results suggest that PI-GO is an attractive candidate for applications in next generation nonvolatile memory.

2021 ◽  
Vol 2021 ◽  
pp. 1-7
Author(s):  
Hau Huu Do Ho ◽  
Trung Minh Le ◽  
Ngoc Kim Pham

Resistive random access memory (RRAM) is emerging as a new class of nonvolatile memory that offers promising electronic properties and simple metal-insulator-metal (MIM) structures for sandwich layers, such as organics, inorganics, and hybrid materials. Hybrid structures have attracted much interest recently because of their advantageous properties. The combination of chitosan (CS) and graphene oxide (GO) acts as switching layers in the Al/CS-GO/FTO RRAM structure it is studied with bipolar switching behavior at approximately 102 ON/OFF ratios during 100 cycles. This hybrid interaction is identified by shifts in the D, G, and 2D bands using Raman spectroscopy. The conduction mechanism is proposed to be a space-charge-limited conduction (SCLC) mechanism and trap-assisted tunneling conduction mechanism in the ON and OFF states, respectively. The trapped and detrapped electrons move through the trap sites with external electric fields, and this movement is responsible for the switching mechanism of the CS-GO nanocomposite memory device.


2015 ◽  
Vol 2015 ◽  
pp. 1-6
Author(s):  
Peng Hai-yun ◽  
Zhou Wen-gang

There are high demands for research of new device with greater accessing speed and stability to replace the current SRAM storage cell. The resistive random access memory (ReRAM) is a metal oxide which is based on nonvolatile memory device possessing the characteristics of high read/write speed, high storage density, low power, low cost, very small cell, being nonvolatile, and unlimited writing endurance. The device has extreme short erasing time and the stored charge cannot be destroyed after power-off. Therefore, the ReRAM device is a significant storage device for many applications in the next generation. In this paper, we first explored the mechanism of the ReRAM device based on ion mobility model and then applied this device to optimize the design of FPGA switching matrix. The results show that it is beneficial to enhance the FPGA performance to replace traditional SRAM cells with ReRAM cells for the switching matrix.


Nanomaterials ◽  
2020 ◽  
Vol 10 (8) ◽  
pp. 1448
Author(s):  
Lei Li

Tristable memristic switching provides the capability for multi-bit data storage. In this study, all-inorganic multi-bit memory devices were successfully manufactured by the attachment of graphene quantum dots (GQDs) onto graphene oxide (GO) through a solution-processable method. By means of doping GQDs as charge-trapping centers, the device indium-tin oxide (ITO)/GO:0.5 wt%GQDs/Ni revealed controllable memristic switching behaviors that were tunable from binary to ternary, and remarkably enhanced in contrast with ITO/GO/Ni. It was found that the device has an excellent performance in memristic switching parameters, with a SET1, SET2 and RESET voltage of −0.9 V, −1.7 V and 5.15 V, as well as a high ON2/ON1/OFF current ratio (103:102:1), and a long retention time (104 s) together with 100 successive cycles. The conduction mechanism of the binary and ternary GO-based memory cells was discussed in terms of experimental data employing a charge trapping-detrapping mechanism. The reinforcement effect of GQDs on the memristic switching of GO through cycle-to-cycle operation has been extensively investigated, offering great potential application for multi-bit data storage in ultrahigh-density, nonvolatile memory.


2020 ◽  
Vol 10 (10) ◽  
pp. 3506
Author(s):  
Nayan C. Das ◽  
Se-I Oh ◽  
Jarnardhanan R. Rani ◽  
Sung-Min Hong ◽  
Jae-Hyung Jang

Resistive random-access memory (RRAM) devices are fabricated by utilizing silicon oxynitride (SiOxNy) thin film as a resistive switching layer. A SiOxNy layer is deposited on a p+-Si substrate and capped with a top electrode consisting of Au/Ni. The SiOxNy-based memory device demonstrates bipolar multilevel operation. It can switch interchangeably between all resistance states, including direct SET switching from a high-resistance state (HRS) to an intermediate-resistance state (IRS) or low-resistance state (LRS), direct RESET switching process from LRS to IRS or HRS, and SET/RESET switching from IRS to LRS or HRS by controlling the magnitude of the applied write voltage signal. The device also shows electroforming-free ternary nonvolatile resistive switching characteristics having RHRS/RIRS > 10, RIRS/RLRS > 5, RHRS/RLRS > 103, and retention over 1.8 × 104 s. The resistive switching mechanism in the devices is found to be combinatory processes of hopping conduction by charge trapping/detrapping in the bulk SiOxNy layer and filamentary switching mode at the interface between the SiOxNy and Ni layers.


2004 ◽  
Vol 830 ◽  
Author(s):  
Jin-Ping Han

ABSTRACTThe quest for a nonvolatile memory FET based on the metal-ferroelectric-(insulator)-semiconductor (MF(I)S) gate stack concept has greatly intensified in recent years. In principle, such a memory device (MF(I)S) could be a building block of an ideal memory technology which offers random access, high speed, low power, high density and non-volatility. In practice, however, none of the reported ferroelectric memory transistors has achieved a memory retention time of more than a few days so far. These results are a far cry from the 10-year retention time requirement for non-volatile memory devices. This paper reveals progress and optimization that grain size, interfacial properties, and crystallinity of the annealed ferroelectric SrBi2Ta2O9 (SBT) films have a strong impact on the size of the memory window, as does the choice of the buffer layer material. The properties of SiN buffer layer sandwiched between SBT and Si are discussed. Switches in the polarization of the ferroelectric SBT play a key role for both the ferroelectric-polarization-dominated and the trapping-dominated memory windows. Preliminary results on MFIS capacitors and transistors are reviewed, limited retention time has been observed. A closer look at the physics of device operation reveals two major causes of the short retention time: (1) depolarization fields; (2) finite gate leakage current and the associated charge trapping. Here, the origins of these problems are analyzed and practical difficulties in attempting to realize nonvolatile ferroelectric 1-T memory devices are illustrated. Two possible solutions have been proposed to circumvent problems associated with the finite retention time in ferroelectric FETtype memories: (1) memory refreshes as done in the FEDRAM cell, (2) single-crystallize the ferroelectric film.


2008 ◽  
Vol 29 (3) ◽  
pp. 265-268 ◽  
Author(s):  
Ping-Hung Tsai ◽  
Kuei-Shu Chang-Liao ◽  
Chu-Yung Liu ◽  
Tien-Ko Wang ◽  
P. J. Tzeng ◽  
...  

2021 ◽  
Vol 12 (7) ◽  
pp. 1876-1884
Author(s):  
Mousam Charan Sahu ◽  
Sameer Kumar Mallik ◽  
Sandhyarani Sahoo ◽  
Sanjeev K. Gupta ◽  
Rajeev Ahuja ◽  
...  

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