scholarly journals A High-Throughput Electrokinetic Micromixer via AC Field-Effect Nonlinear Electroosmosis Control in 3D Electrode Configurations

Micromachines ◽  
2018 ◽  
Vol 9 (9) ◽  
pp. 432 ◽  
Author(s):  
Kai Du ◽  
Weiyu Liu ◽  
Yukun Ren ◽  
Tianyi Jiang ◽  
Jingni Song ◽  
...  
Keyword(s):  
Field Effect ◽  
Bottom Surface ◽  
Microfluidic Mixing ◽  
New Device ◽  
Experimental Parameters ◽  
Voltage Wave ◽  
Effect Transistor ◽  
Ac Field ◽  
Channel Bottom ◽  
3D Electrode

In this study, we make use of the AC field-effect flow control on induced-charge electroosmosis (ICEO), to develop an electrokinetic micromixer with 3D electrode layouts, greatly enhancing the device performance compared to its 2D counterpart of coplanar metal strips. A biased AC voltage wave applied to the central gate terminal, i.e., AC field-effect control, endows flow field-effect-transistor of ICEO the capability to produce arbitrary symmetry breaking in the transverse electrokinetic vortex flow pattern, which makes it fascinating for microfluidic mixing. Using the Debye-Huckel approximation, a mathematical model is established to test the feasibility of the new device design in stirring nanoparticle samples carried by co-flowing laminar streams. The effect of various experimental parameters on constructing a viable micromixer is investigated, and an integrated microdevice with a series of gate electrode bars disposed along the centerline of the channel bottom surface is proposed for realizing high-flux mixing. Our physical demonstration on field-effect nonlinear electroosmosis control in 3D electrode configurations provides useful guidelines for electroconvective manipulation of nanoscale objects in modern microfluidic systems.

scholarly journals Optimization of Line-Tunneling Type L-Shaped Tunnel Field-Effect-Transistor for Steep Subthreshold Slope

Electronics ◽  
2018 ◽  
Vol 7 (11) ◽  
pp. 275 ◽  
Author(s):  
Faraz Najam ◽  
Yun Yu
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Field Effect Transistors ◽  
Oxide Semiconductor ◽  
Subthreshold Slope ◽  
Corner Effect ◽  
New Device ◽  
Optimum Configuration ◽  
Effect Transistor ◽  
Dual Material

The L-shaped tunneling field-effect-transistor (LTFET) has been recently introduced to overcome the thermal subthreshold limit of conventional metal-oxide-semiconductor field-effect-transistors (MOSFET). In this work, the shortcomings of the LTFET was investigated. It was found that the corner effect present in the LTFET effectively degrades its subthreshold slope. To avoid the corner effect, a new type of device with dual material gates is presented. The new device, termed the dual-gate (DG) LTEFT (DG-LTFET), avoids the corner effect and results in a significantly improved subthreshold slope of less than 10 mV/dec, and an improved ON/OFF current ratio over the LTFET. The DG-LTFET was evaluated for different device parameters and bench-marked against the LTFET. This work presents the optimum configuration of the DG-LTFET in terms of device dimensions and doping levels to determine the best subthreshold, ON current, and ambipolar performance.

scholarly journals Review of Nanosheet Transistors Technology

2021 ◽  
Vol 28 (1) ◽  
pp. 40-48
Author(s):  
Firas Agha ◽  
Yasir Naif ◽  
Mohammed Shakib
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Metal Gate ◽  
Nano Structure ◽  
New Device ◽  
Technology Node ◽  
Structure Of Metal ◽  
Effect Transistor

Nano-sheet transistor can be defined as a stacked horizontally gate surrounding the channel on all direction. This new structure is earning extremely attention from research to cope the restriction of current Fin Field Effect Transistor (FinFET) structure. To further understand the characteristics of nano-sheet transistors, this paper presents a review of this new nano-structure of Metal Oxide Semiconductor Field Effect Transistor (MOSFET), this new device that consists of a metal gate material. Lateral nano-sheet FET is now targeting for 3nm Complementary MOS (CMOS) technology node. In this review, the structure and characteristics of Nano-Sheet FET (NSFET), FinFET and NanoWire FET (NWFET) under 5nm technology node are presented and compared. According to the comparison, the NSFET shows to be more impregnable to mismatch in ON current than NWFET. Furthermore, as comparing with other nanodimensional transistors, the NSFET has the superior control of gate all-around structures, also the NWFET realize lower mismatch in sub threshold slope (SS) and drain induced barrier lowering (DIBL).

A computational study of a novel graphene nanoribbon field effect transistor

2017 ◽  
Vol 31 (09) ◽  
pp. 1750056 ◽  
Author(s):  
Seyed Saleh Ghoreishi ◽  
Reza Yousefi
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Computational Study ◽  
Graphene Nanoribbon ◽  
New Device ◽  
Gate Structure ◽  
Dopant Profile ◽  
Effect Transistor ◽  
Switching Characteristics ◽  
Power Delay Product

In this paper, using gate structure engineering and modification of channel dopant profile, we propose a new double gate graphene nanoribbon field effect transistor (DG-GNRFET) mainly to suppress the band-to-band tunneling (BTBT) of carriers. In the new device, the intrinsic part of the channel is replaced by an intrinsic-lightly doped-intrinsic [Formula: see text] configuration in a way that only the intrinsic parts are covered by the gate contact. Transport characteristics of the device are investigated theoretically using the nonequilibrium Green’s function (NEGF) formalism. Numerical simulations show that off-current, ambipolar behavior, on/off-current ratio and the switching characteristics such as intrinsic delay and power-delay product are improved. In addition, the new device demonstrates better sub-threshold swing and less drain-induced barrier lowering (DIBL).

scholarly journals The Balancing Act in Ferroelectric Transistors: How Hard Can It Be?

Micromachines ◽  
2018 ◽  
Vol 9 (11) ◽  
pp. 582 ◽  
Author(s):  
Raymond Hueting
Keyword(s):  
Lead Zirconate Titanate ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Ferroelectric Material ◽  
Ferroelectric Materials ◽  
Polarization Field ◽  
Maximum Speed ◽  
Negative Capacitance ◽  
New Device ◽  
Effect Transistor

For some years now, the ever continuing dimensional scaling has no longer been considered to be sufficient for the realization of advanced CMOS devices. Alternative approaches, such as employing new materials and introducing new device architectures, appear to be the way to go forward. A currently hot approach is to employ ferroelectric materials for obtaining a positive feedback in the gate control of a switch. This work elaborates on two device architectures based on this approach: the negative-capacitance and the piezoelectric field-effect transistor, i.e., the NC-FET (negative-capacitance field-effect transistor), respectively π -FET. It briefly describes their operation principle and compares those based on earlier reports. For optimal performance, the adopted ferroelectric material in the NC-FET should have a relatively wide polarization-field loop (i.e., “hard” ferroelectric material). Its optimal remnant polarization depends on the NC-FET architecture, although there is some consensus in having a low value for that (e.g., HZO (Hafnium-Zirconate)). π -FET is the piezoelectric coefficient, hence its polarization-field loop should be as high as possible (e.g., PZT (lead-zirconate-titanate)). In summary, literature reports indicate that the NC-FET shows better performance in terms of subthreshold swing and on-current. However, since its operation principle is based on a relatively large change in polarization the maximum speed, unlike in a π -FET, forms a big issue. Therefore, for future low-power CMOS, a hybrid solution is proposed comprising both device architectures on a chip where hard ferroelectric materials with a high piezocoefficient are used.

A Method Study on Assembly of Single-Wall Carbon Nanotube Field Effect Transistor Using Dielectrophoresis

2010 ◽  
Vol 139-141 ◽  
pp. 1550-1553 ◽  
Author(s):  
Ke Xu ◽  
Cheng Dong Wu ◽  
Xiao Jun Tian ◽  
Ying Zhang ◽  
Zai Li Dong
Keyword(s):  
Carbon Nanotube ◽  
Electric Field ◽  
Field Effect ◽  
Field Effect Transistor ◽  
Building Blocks ◽  
Single Wall Carbon Nanotubes ◽  
Single Wall Carbon ◽  
Nanoscale Electronics ◽  
Experimental Parameters ◽  
Effect Transistor

Single-wall carbon nanotubes are candidates for a number of building blocks in nanoscale electronics. With respect to the assembly of carbon nanotube field effect transistor, the dielectrophoresis technology is adopted, which assembles SWCNTs between the micro-electrodes, SWCNTs are affected by the electrophoretic force which is carried out by the related theoretical analysis in a nonuniform electric field. The driving electric field of dielectrophoresis is simulated by the comsol software. According to the simulation results, a number of the experiments are done. It turns out that the required experimental parameters of the efficient assembly of SWCNT were obtained. AFM scanning and electrical properties of SWCNTs show that the method can achieve the effective assembly of carbon nanotube field effect transistor. SWCNTs are driven in the microelectrode gap, having a good arrangement of uniform orientation and assembly results, and proportional to the arrangement density along the electrode width direction and the duration of DEP. Meanwhile, it also provides an effective method of assembly and manufacture for other one-dimensional nanomaterials assembly of nanoelectronic devices.

Nano-wire field-effect transistor in etched ion tracks of flexible polymer foils

2003 ◽  
Vol 777 ◽  
Author(s):  
Jie Chen ◽  
S. Klaumünzer ◽  
R. Könenkamp
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Large Area ◽  
New Device ◽  
Stage Of Development ◽  
Flexible Polymer ◽  
Polymer Metal ◽  
Effect Transistor ◽  
Vertical Field Effect ◽  
Soft Polymer

AbstractWe have used irradiation by fast heavy ions and subsequent etching to prepare cylindrical channels in polymer/metal/polymer stacks. These channels were subsequently filled with insulator and semiconductor material, and then provided with suitable metallic contacts, to obtain a vertical field-effect transistor device. Preparation and first electronic results on this new device are reported. Typically 107 to 108 transistors per cm2 with a diameter of ∼100 nm can be obtained in this technique. The fabrication does not require lithography on the scale of a single transistor, and is suitable for large-area applications. The embedding in a soft polymer matrix results in a robust arrangement, whose electronic characteristics are largely insensitive to mechanical stress. At the present stage of development the smallest dimension of a single transistor grown by this technique is ∼50 nm. Further reduction of the device dimensions appears possible and, with it, observation of single electron effects in these devices.

scholarly journals An Experimental Study of 3D Electrode-Facilitated Particle Traffic Flow-Focusing Driven by Induced-Charge Electroosmosis

Micromachines ◽  
2019 ◽  
Vol 10 (2) ◽  
pp. 135 ◽  
Author(s):  
Tianyi Jiang ◽  
Ye Tao ◽  
Hongyuan Jiang ◽  
Weiyu Liu ◽  
Yansu Hu ◽  
...  
Keyword(s):  
Microfluidic Device ◽  
Yeast Cells ◽  
Bottom Surface ◽  
Flow Focusing ◽  
Electrode Strip ◽  
Geometry Configuration ◽  
Particle Stream ◽  
Induced Charge ◽  
Channel Bottom ◽  
3D Electrode

In this paper we present a novel microfluidic approach for continuous, rapid and switchable particle concentration, using induced-charge electroosmosis (ICEO) in 3D electrode layouts. Field-effect control on non-linear electroosmosis in the transverse direction greatly facilitates a selective concentration of biological yeast cells from a straight main microchannel into one of the three downstream branch channels in our microfluidic device. For the geometry configuration of 3D driving electrode plates on sidewalls and a 2D planar gate electrode strip on the channel bottom surface, we briefly describe the underlying physics of an ICEO-based particle flow-focusing method, and provide relevant simulation results to show how gate voltage amplitude can be used to guide the motion trajectory of the concentrated particle stream. With a relatively simple geometrical configuration, the proposed microfluidic device provides new possibilities to controllably concentrate micro/nanoparticles in continuous flow by using ICEO, and is suitable for a high-throughput front-end cell concentrator interfacing with various downstream biosensors.

scholarly journals Study of a New Device Structure: Graphene Field Effect Transistor (GFET)

2021 ◽  
Vol 13 (4) ◽  
pp. 04021-1-04021-5
Author(s):  
P. Vimala ◽  
◽  
Manjunath Bassapuri ◽  
C. R. Harshavardhan ◽  
P. Harshith ◽  
...  
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Device Structure ◽  
New Device ◽  
Graphene Field Effect Transistor ◽  
Effect Transistor

Vertical Nanowire Field Effect Transistor in the Flexible Polymer Foils Based on Ion Tracks

2007 ◽  
Vol 121-123 ◽  
pp. 507-512
Author(s):  
J. Chen ◽  
R. Könenkamp ◽  
S. Klaumünzer ◽  
M.Ch. Lux-Steiner
Keyword(s):  
Field Effect ◽  
Field Effect Transistor ◽  
Large Area ◽  
New Device ◽  
Ion Tracks ◽  
Flexible Polymer ◽  
Effect Transistor ◽  
Vertical Field Effect ◽  
Polymer Foils ◽  
Pet Foils

Fabrication of flexible device structures and nanoscale size definition are presently among the most important and ambitious development goals in the IT field. We have recently prepared the vertical nanowire field effect transistor in the flexible polymer foils based on ion tracks. The high-energetic fast heavy ions were used to irradiate the 8μm PET foils and then the chemical etching method were employed to prepare cylindrical channels in these PET foils. These channels were subsequently filled with insulator material and semiconductor, and then provided with suitable metallic contacts, to obtain a vertical field-effect transistor device. Preparation and first electronic results on this new device are reported. Typically over 107 transistors per cm2 with the devices’ diameter of ~100 nm can be obtained in this technique. The fabrication does not require lithography on the scale of a single transistor, and is suitable for large-area and flexible applications.

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