scholarly journals Eco-Friendly Lead-Free Solder Paste Printing via Laser-Induced Forward Transfer for the Assembly of Ultra-Fine Pitch Electronic Components

Materials ◽  
2021 ◽  
Vol 14 (12) ◽  
pp. 3353
Author(s):  
Marina Makrygianni ◽  
Filimon Zacharatos ◽  
Kostas Andritsos ◽  
Ioannis Theodorakos ◽  
Dimitris Reppas ◽  
...  
Keyword(s):  
High Resolution ◽  
Form Factors ◽  
Circuit Board ◽  
Lead Free ◽  
Process Conditions ◽  
Solder Paste ◽  
Electronic Components ◽  
Successful Operation ◽  
Fine Pitch ◽  
Forward Transfer

Current challenges in printed circuit board (PCB) assembly require high-resolution deposition of ultra-fine pitch components (<0.3 mm and <60 μm respectively), high throughput and compatibility with flexible substrates, which are poorly met by the conventional deposition techniques (e.g., stencil printing). Laser-Induced Forward Transfer (LIFT) constitutes an excellent alternative for assembly of electronic components: it is fully compatible with lead-free soldering materials and offers high-resolution printing of solder paste bumps (<60 μm) and throughput (up to 10,000 pads/s). In this work, the laser-process conditions which allow control over the transfer of solder paste bumps and arrays, with form factors in line with the features of fine pitch PCBs, are investigated. The study of solder paste as a function of donor/receiver gap confirmed that controllable printing of bumps containing many microparticles is feasible for a gap < 100 μm from a donor layer thickness set at 100 and 150 μm. The transfer of solder bumps with resolution < 100 μm and solder micropatterns on different substrates, including PCB and silver pads, have been achieved. Finally, the successful operation of a LED interconnected to a pin connector bonded to a laser-printed solder micro-pattern was demonstrated.

Comparative Modeling and Analysis of Lead-Free Solder Extrusion for the Design of Reliability

2016 ◽  
Vol 2016 (1) ◽  
pp. 000111-000116
Author(s):  
Youngtak Lee ◽  
Doug Link
Keyword(s):  
Design Of Experiments ◽  
Flip Chip ◽  
Failure Modes ◽  
Form Factors ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Modeling And Analysis ◽  
Surface Mount ◽  
Free Solder

Abstract Due to rapid growth of the microelectronics industry, packaged devices with small form factors, low costs, high power performance, and increased efficiency have become of high demand in the market. To realize the current market development trend, flip chip interconnection and System-in-Package (SiP) are some of the promising packaging solutions developed. However, a surprising amount of surface mount technology (SMT) defects are associated with the use of lead-free solder paste and methods by which the paste is applied. Two such defects are solder extrusion and tombstoning. Through the use of design of experiments (DOE), lead-free solder defect causes can be better understood and subsequently reduced or eliminated. This paper will examine the failure modes of solder extrusion and tombstoning that occurred when two different types of lead-free solders, Sn-Ag-Cu (SAC) and BiAgX were used within a SiP for attachment of surface mount devices (SMD) chip components. The systematic investigation will include the comprehensive failure analysis of the SMD components and compare the modeling and analysis of the two different solder types utilizing the design of experiments methods.

Site Redressing Techniques and Rework of Lead-Free Chip Scale Packages

2003 ◽  
Author(s):  
Arun Gowda ◽  
Anthony Primavera ◽  
K. Srihari
Keyword(s):  
Printed Circuit Board ◽  
Circuit Board ◽  
Lead Free ◽  
Lead Free Solder ◽  
Solder Paste ◽  
Printed Circuit ◽  
Free Solder ◽  
The Individual ◽  
Component Assembly ◽  
Free Area

The implementation of lead-free solder into an electronics assembly process necessitates the reassessment of the individual factors involved in component attachment and rework. A component assembly undergoes multiple thermal cycles during rework. With the use of lead-free solder, the assemblies are subjected to higher assembly and rework temperatures than those required for eutectic tin-lead assemblies. The rework of lead-free area array components involves the removal of defective component, preparation of the printed circuit board attachment pad (site redressing), solder paste replenishment or flux deposition, and component placement and reflow. This paper primarily focuses on the site redressing aspect of lead-free rework, followed by the development of rework processes for lead-free chip scale packages utilizing the knowledge gained in the site redressing studies.

A Repeatable and Reliable Rework Process for Lead-Free Fine Pitch BGA’s

2005 ◽  
Author(s):  
Deepak Manjunath ◽  
Satyanarayan Iyer ◽  
Shawn Eckel ◽  
Purushothaman Damodaran ◽  
Krishnaswami Srihari
Keyword(s):  
Primary Objective ◽  
Lead Free ◽  
Process Window ◽  
Solder Paste ◽  
Ball Grid Arrays ◽  
Joint Reliability ◽  
Fine Pitch ◽  
Pros And Cons ◽  
Free Solder ◽  
Rework Process

Fine pitch leadless components, such as Ball Grid Arrays (BGAs) and Chip-Scale Packages (CSPs), are increasingly used in modern day circuitry to aid miniaturization. Assembling these surface mount components using lead-free solder pastes has been a subject of interest for the past several years. Reworking a BGA is complicated as the solder joints are hidden underneath the component. The process window available for the rework process is very narrow and there are number of other critical factors, which complicate and affect the repeatability of the rework process. Consequently, the primary objective of this research endeavor is to develop a reliable and a repeatable process to rework lead-free fine pitch BGAs. The process steps to rework a BGA are component removal, site redressing, solder paste/flux deposition, component replacement and reflow. This experimental study evaluates a number of alternatives for several rework process steps during the course of developing a reliable and repeatable rework process. Two alternatives for site redressing namely, (i) copper wick with soldering iron, and (ii) vacuum de-soldering methods are evaluated. Similarly the application of solder paste versus gel flux is compared. A localized reflow method for replacing the component at the SRT machine is developed and it is compared with forced convection in reflow oven. The pros and cons of using the two reflow methods and the effect of multiple reflows on solder joint reliability is discussed in the paper. A reliability study was conducted on the samples and the results are presented to compare the various alternatives.

Super Fine Lead-Free Solder Powder for Fine Pitch Bump Applications

2012 ◽  
Vol 2012 (DPC) ◽  
pp. 001016-001038
Author(s):  
Ryuji Uesugi ◽  
Hironori Uno ◽  
Masayuki Ishikawa ◽  
Akihiro Masuda ◽  
Hiroki Muraoka ◽  
...  
Keyword(s):  
Chemical Reduction ◽  
Fine Powder ◽  
Lead Free ◽  
High Yield ◽  
Solder Paste ◽  
Fine Pitch ◽  
Solder Bumps ◽  
Wet Chemical ◽  
Free Solder ◽  
Near Future

We have successfully developed super fine lead-free and low alpha solder powder, which contains more than two elements by the method of wet chemical reduction. The size (D50) of super fine powder is around 2–3 micrometer to meet finer pitch assembly in the near future. This new method made it available to synthesize various compositions of solder powder like Sn-Ag, Sn-Cu, Sn-Ag-Cu, etc. Also, this method achieves very high yield compared to a gas atomization method. A solder paste for printing method composed of the fine solder powder has a superior printing ability because of the unique powder shape. The powder shows anisotropic shape, and it can make printed figure excellent after printing without bridge and coplanarity issues for finer pitch applications. With our super fine solder paste, we will be ready for &lt;100um pitch of solder bumps which will come in a few years. Furthermore, the super fine powder is applied to the Cu pad pre-coat. The solder paste for pre-coat composed of the super fine powder shows an excellent coverage and solders flatness on the outer pad after reflow.

The Impact of Stencil Printing Upon Assembly & Reliability Of 0.3mm Pitch CSP Components

2016 ◽  
Vol 2016 (1) ◽  
pp. 000667-000674
Author(s):  
Mark Whitmore ◽  
Jeff Schake
Keyword(s):  
Form Factors ◽  
Preliminary Test ◽  
Process Window ◽  
Solder Paste ◽  
Electronic Assembly ◽  
Stencil Printing ◽  
Printing Process ◽  
Fine Pitch ◽  
Technology Standard ◽  
The Impact

Abstract With the continual shrinking of electronic assembly form factors, designers are being forced towards smaller, more complex components with decreasing interconnection pitches. As a consequence, the Surface Mount assembly process is becoming increasingly challenged. For the stencil printing process, this means that historically accepted stencil aperture area ratio design rules, (which dictate what can or cannot be printed), need to be significantly pushed to extend the printing process for next generation ultra -fine pitch components. As a result, a major study has been undertaken looking at several different aspects of the stencil printing process, and their impact upon the assembly and reliability of 0.3mm pitch CSP components. In a preliminary test, stencil printing factors such as stencil aperture size and printing technology (standard squeegees vs ultrasonically aided active squeegees) were investigated. Data showed that the active squeegees provided a significantly larger process window. Subsequently, components were assembled using a range of solder paste volumes printed with both standard and active squeegee technology. The components assembled using an active squeegee process exhibited higher assembly yield, and also extended reliability when subjected to thermal cycling.

A Novel Additive Manufacturing File Format for Printed Electronics

2013 ◽  
Author(s):  
Neeraj Panhalkar ◽  
Ratnadeep Paul ◽  
Sam Anand
Keyword(s):  
Additive Manufacturing ◽  
Large Scale ◽  
Printed Electronics ◽  
Form Factors ◽  
Circuit Board ◽  
File Format ◽  
Electronic Components ◽  
Direct Printing ◽  
Manufacturing Information ◽  
The Cost

Additive Manufacturing (AM) based Printed Electronics (PE) is an emerging technique where electronic components and interconnects are printed directly on substrates using a layered technique. The direct printing of the electronic components allows large scale and ultra-thin components to be printed on a wide variety of substrates including glass, silicon and plastic. These attributes make AM based Printed Electronics an invaluable manufacturing technique in the area of electronic sensors and sensor networks where thin, flexible and rugged form factors are very important. However, currently this technology is a labor intensive and manual process with the machine operator using his experience and judgment to slice the CAD file of the part to create 2D layers at different levels. This manual process increases the overall production time as well as the cost of the product and also results in inconsistent quality of parts. A major challenge faced by existing AM based Printed Electronics users for automating this process is the lack of a standard input file format that can be used by different PE machines for producing the components in layers. To leverage the capabilities of both AM and PE processes, a new file format based on the Constructive Solid Geometry (CSG) technique is proposed in this research paper. This file format data will not only include CAD data in the form of CSG primitives and Boolean representation but will also include manufacturing information related to the AM based PE process. The manufacturing information embedded within this new format will include data about the location of the different electronic components such as interconnects, resistors, capacitors, inductors, transistors, memory and substrate, and the materials required for the different components part. Different circuit board components will be represented as primitives or a combination of primitives obtained using CSG technique. In addition to the new file format, a slicing algorithm will also be developed which can be used to create the layers automatically using user inputs. The proposed file format and the slicing algorithm will be explained with the help of a case study.

Rheology Characterization of Solder Paste

2017 ◽  
Author(s):  
Flávia V. Barbosa ◽  
Pedro E. A. Ribeiro ◽  
Maria F. Cerqueira ◽  
Delfim F. Soares ◽  
José C. F. Teixeira ◽  
...  
Keyword(s):  
Shear Rate ◽  
Production Efficiency ◽  
Printed Circuit Board ◽  
Circuit Board ◽  
Creep Recovery ◽  
Solder Paste ◽  
Electronic Components ◽  
Increase Production Efficiency ◽  
Reflow Soldering ◽  
Soldering Process

Reflow soldering process is widely implemented in the electronics industry. This method allows the attachment of electronic components to a printed circuit board (PCB) through the melting of solder paste, which makes the interconnection between them. The reflow soldering process must ensures the correctly melting of the solder paste and heating of the adjoining surfaces, without the electronic components suffer overheating or any other type of damage. Solder paste is the most widespread material in the SMT (Surface Mount Technology) process using reflow soldering. An ideal solder paste will increase production efficiency, decreasing the amount of defects associated with the reflow soldering process. However, several factors affects the performance of the solder paste, from rheology, printability, and reliability to the adhesion strength of components and the ability to avoid defects related to reflow. Therefore, all these factors need to be considered during the selection of a solder paste for a specific application. The rheological properties were determined using both a double cylinder (PHYSICA-RHEOLAB MC1) and a double plate (Malvern) rheometers. The later enable the determination of viscoelastic properties. The present paper analyses the rheological behavior of a SAC405 solder paste, a mixture containing a metal alloy powder (25–45 μm) and a flux which at its base is a resin. The tests were carried out at conditions (temperature and shear rate) of relevance to the printing process. The results obtained show that the paste viscosity closely follows the Herschel-Bulkley model and shows a thixotropic behavior without fully recovery between applications. In addition, the viscosity decreases with the increase of shear rate confirming that the solder paste is a non-Newtonian fluid, shear thinning in behavior. The oscillatory tests have shown that the transition from elastic to viscous behavior occurs at a shear stress above 35 Pa. On the other hand, the creep/recovery test confirms that the level of solicitation influences the capacity of recovery of the solder paste.

Data Center Equipment Reliability Concerns—Contamination Issues, Standards Actions, and Case Studies

2013 ◽  
Author(s):  
Chris Muller ◽  
Chuck Arent ◽  
Henry Yu
Keyword(s):  
Case Studies ◽  
Data Center ◽  
Data Centers ◽  
Electronic Equipment ◽  
Circuit Board ◽  
Lead Free ◽  
Reliable Operation ◽  
Contamination Assessment ◽  
Equipment Reliability ◽  
Equipment Failures

Abstract Lead-free manufacturing regulations, reduction in circuit board feature sizes and the miniaturization of components to improve hardware performance have combined to make data center IT equipment more prone to attack by corrosive contaminants. Manufacturers are under pressure to control contamination in the data center environment and maintaining acceptable limits is now critical to the continued reliable operation of datacom and IT equipment. This paper will discuss ongoing reliability issues with electronic equipment in data centers and will present updates on ongoing contamination concerns, standards activities, and case studies from several different locations illustrating the successful application of contamination assessment, control, and monitoring programs to eliminate electronic equipment failures.

Materials Characterization of Lead Free Compositions for Minimum Temperature SMT Processes at the SLI-Second Level Interconnect Solder Joint

2004 ◽  
Author(s):  
Norman J. Armendariz ◽  
Prawin Paulraj
Keyword(s):  
Solder Joint ◽  
Printed Circuit Board ◽  
Gold Surface ◽  
Circuit Board ◽  
Lead Free ◽  
Processing Temperature ◽  
The European Union ◽  
Printed Circuit ◽  
Higher Temperature ◽  
Tin Silver Copper

Abstract The European Union is banning the use of Pb in electronic products starting July 1st, 2006. Printed circuit board assemblies or “motherboards” require that planned CPU sockets and BGA chipsets use lead-free solder ball compositions at the second level interconnections (SLI) to attach to a printed circuit board (PCB) and survive various assembly and reliability test conditions for end-use deployment. Intel is pro-actively preparing for this anticipated Pb ban, by evaluating a new lead free (LF) solder alloy in the ternary Tin- Silver-Copper (Sn4.0Ag0.5Cu) system and developing higher temperature board assembly processes. This will be pursued with a focus on achieving the lowest process temperature required to avoid deleterious higher temperature effects and still achieve a metallurgically compatible solder joint. One primary factor is the elevated peak reflow temperature required for surface mount technology (SMT) LF assembly, which is approximately 250 °C compared to present eutectic tin/lead (Sn37Pb) reflow temperatures of around 220 °C. In addition, extended SMT time-above-liquidus (TAL) and subsequent cooling rates are also a concern not only for the critical BGA chipsets and CPU BGA sockets but to other components similarly attached to the same PCB substrate. PCBs used were conventional FR-4 substrates with organic solder preservative on the copper pads and mechanical daisychanged FCBGA components with direct immersion gold surface finish on their copper pads. However, a materials analysis method and approach is also required to characterize and evaluate the effect of low peak temperature LF SMT processing on the PBA SLI to identify the absolute limits or “cliffs” and determine if the minimum processing temperature and TAL could be further lowered. The SLI system is characterized using various microanalytical techniques, such as, conventional optical microscopy, scanning electron microscopy, energy dispersive spectroscopy and microhardness testing. In addition, the SLI is further characterized using macroanalytical techniques such as dye penetrant testing (DPT) with controlled tensile testing for mechanical strength in addition to disbond and crack area mapping to complete the analysis.

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