scholarly journals Effect of Simultaneous Mechanical and Electrical Stress on the Electrical Performance of Flexible In-Ga-Zn-O Thin-Film Transistors

Materials ◽  
2019 ◽  
Vol 12 (19) ◽  
pp. 3248 ◽  
Author(s):  
Youngjin Seo ◽  
Hwan-Seok Jeong ◽  
Ha-Yun Jeong ◽  
Shinyoung Park ◽  
Jun Tae Jang ◽  
...  
Keyword(s):  
Thin Film ◽  
Mechanical Stress ◽  
Thin Film Transistors ◽  
Hydrogen Diffusion ◽  
Atomic Layer ◽  
Electrical Performance ◽  
Bending Stress ◽  
Threshold Voltage Shift ◽  
Electrical Stress ◽  
Mechanical Bending

We investigated the effect of simultaneous mechanical and electrical stress on the electrical characteristics of flexible indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs). The IGZO TFTs exhibited a threshold voltage shift (∆VTH) under an application of positive-bias-stress (PBS), with a turnaround behavior from the positive ∆VTH to the negative ∆VTH with an increase in the PBS application time, whether a mechanical stress is applied or not. However, the magnitudes of PBS-induced ∆VTH in both the positive and negative directions exhibited significantly larger values when a flexible IGZO TFT was under mechanical-bending stress than when it was at the flat state. The observed phenomena were possibly attributed to the mechanical stress-induced interface trap generation and the enhanced hydrogen diffusion from atomic layer deposition-grown Al2O3 to IGZO under mechanical-bending stress during PBS. The subgap density of states was extracted before and after an application of PBS under both mechanical stress conditions. The obtained results in this study provided potent evidence supporting the mechanism suggested to explain the PBS-induced larger ∆VTHs in both directions under mechanical-bending stress.

scholarly journals Tuning the electrical performance and bias stability of a semiconducting SWCNT thin film transistor with an atomic layer deposited AlZrOx composite

RSC Advances ◽  
2017 ◽  
Vol 7 (83) ◽  
pp. 52517-52523 ◽  
Author(s):  
Jun Li ◽  
Chuan-Xin Huang ◽  
Jian-Hua Zhang
Keyword(s):  
Thin Film ◽  
Carbon Nanotube ◽  
Thin Film Transistors ◽  
Thin Film Transistor ◽  
Atomic Layer ◽  
Electrical Performance ◽  
Solution Processed ◽  
Single Walled Carbon Nanotube ◽  
Single Walled Carbon ◽  
Bias Stability

Solution-processed semiconducting single-walled carbon nanotube (s-SWCNT) thin film transistors (TFTs) based on different atomic layer deposited AlZrOx insulators are fabricated and characterized.

scholarly journals Electrical Performance and Stability Improvement of p-Channel SnO Thin-Film Transistors Using Atomic-Layer-Deposited Al₂O₃ Capping Layer

IEEE Access ◽  
2020 ◽  
Vol 8 ◽  
pp. 222410-222416
Author(s):  
Kang-Hwan Bae ◽  
Min Gyu Shin ◽  
Seong-Hyun Hwang ◽  
Hwan-Seok Jeong ◽  
Dae-Hwan Kim ◽  
...  
Keyword(s):  
Thin Film ◽  
Thin Film Transistors ◽  
Atomic Layer ◽  
Electrical Performance ◽  
Capping Layer

scholarly journals A Study on Solution-Processed Y2O3 Films Modified by Atomic Layer Deposition Al2O3 as Dielectrics in ZnO Thin Film Transistor

Coatings ◽  
2021 ◽  
Vol 11 (8) ◽  
pp. 969
Author(s):  
Haiyang Xu ◽  
Xingwei Ding ◽  
Jie Qi ◽  
Xuyong Yang ◽  
Jianhua Zhang
Keyword(s):  
Thin Film ◽  
Atomic Layer Deposition ◽  
Active Layer ◽  
Dielectric Layer ◽  
Thin Film Transistor ◽  
Atomic Layer ◽  
Electrical Performance ◽  
Zno Thin Film ◽  
Threshold Voltage Shift ◽  
Layer Deposition

In this work, Y2O3–Al2O3 dielectrics were prepared and used in ZnO thin film transistor as gate insulators. The Y2O3 film prepared by the sol–gel method has many surface defects, resulting in a high density of interface states with the active layer in TFT, which then leads to poor stability of the devices. We modified it by atomic layer deposition (ALD) technology that deposited a thin Al2O3 film on the surface of a Y2O3 dielectric layer, and finally fabricated a TFT device with ZnO as the active layer by ALD. The electrical performance and bias stability of the ZnO TFT with a Y2O3–Al2O3 laminated dielectric layer were greatly improved, the subthreshold swing was reduced from 147 to 88 mV/decade, the on/off-state current ratio was increased from 4.24 × 106 to 4.16 × 108, and the threshold voltage shift was reduced from 1.4 to 0.7 V after a 5-V gate was is applied for 800 s.

Threshold voltage shift under electrical stress in amorphous, polymorphous, and microcrystalline silicon bottom gate thin-film transistors

2009 ◽  
Vol 207 (5) ◽  
pp. 1245-1248 ◽  
Author(s):  
Maher Oudwan ◽  
Oumkelthoum Moustapha ◽  
Alexey Abramov ◽  
Dmitriy Daineka ◽  
Yvan Bonnassieux ◽  
...  
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Microcrystalline Silicon ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Electrical Stress ◽  
Bottom Gate

Threshold Voltage Shift Variation of a-Si:H TFTs With Anneal Time

2010 ◽  
Vol 1245 ◽  
Author(s):  
Anil Indluru ◽  
Sameer M Venugopal ◽  
David R Allee ◽  
Terry L Alford
Keyword(s):  
Thin Film ◽  
Threshold Voltage ◽  
Thin Film Transistors ◽  
Liquid Crystal Display ◽  
Electrical Performance ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Active Matrix ◽  
Improved Performance ◽  
Anneal Time

AbstractHydrogenated amorphous silicon (a-Si:H) thin-film transistors (TFTs) are widely used in many areas and the most important application is in active matrix liquid crystal display. However, the instability of the a-Si:H TFTs constrains their usability. These TFTs have been annealed at higher temperatures in hope of improving their electrical performance. But, higher anneal temperatures become a constraint when the TFTs are grown on polymer-based flexible substrates. This study investigates the effect of anneal time on the performance of the a-Si:H TFTs on PEN. Thin-film transistors are annealed at different anneal times (4 h, 24 h, and 48 h) and were stressed under different bias conditions. Sub-threshold slope and the off-current improved with anneal time. Off-current was reduced by two orders of magnitude for 48 hours annealed TFT and sub-threshold slope became steeper with longer annealing. At positive gate-bias-stress (20 V), threshold voltage shift (∆Vt) values are positive and exhibit a power-law time dependence. High temperature measurements indicate that longer annealed TFTs show improved performance and stability compared to unannealed TFTs. This improvement is due to reduction of interface trap density and good a-Si:H/insulator interface quality with anneal time.

scholarly journals Effect of hydrogen diffusion in an In–Ga–Zn–O thin film transistor with an aluminum oxide gate insulator on its electrical properties

RSC Advances ◽  
2018 ◽  
Vol 8 (10) ◽  
pp. 5622-5628 ◽  
Author(s):  
Yunyong Nam ◽  
Hee-Ok Kim ◽  
Sung Haeng Cho ◽  
Sang-Hee Ko Park
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Aluminum Oxide ◽  
Thin Film Transistors ◽  
Hydrogen Diffusion ◽  
Thin Film Transistor ◽  
Atomic Layer ◽  
Gate Insulator ◽  
Layer Deposition ◽  
Amorphous Ingazno

We fabricated amorphous InGaZnO thin film transistors (a-IGZO TFTs) with aluminum oxide (Al2O3) as a gate insulator grown through atomic layer deposition (ALD) method at different deposition temperatures (Tdep).

Electrical Properties of Solution Processed In–Ga–ZnO Thin Film Transistors with Multi-Stacked Active Layer

2015 ◽  
Vol 15 (10) ◽  
pp. 7508-7512 ◽  
Author(s):  
Soon Kon Kim ◽  
Pyung Ho Choi ◽  
Sang Sub Kim ◽  
Hyun Woo Kim ◽  
Na Young Lee ◽  
...  
Keyword(s):  
Thin Film ◽  
Electrical Properties ◽  
Active Layer ◽  
Thin Film Transistors ◽  
High Mobility ◽  
Electrical Performance ◽  
Zno Thin Film ◽  
Threshold Voltage Shift ◽  
Active Layers ◽  
Current Path

In this study, we prepared solution-based In–Ga–ZnO thin film transistors (IGZO TFTs) having a multistacked active layer. The solution was prepared using an In:Zn = 1:1 mole ratio with variation in Ga content, and the TFTs were fabricated by stacking layers from the prepared solutions. After we measured the mobility of each stacked layer, the saturation mobility showed values of 0.8, 0.6 and 0.4 (cm2/Vs), with an overall decrease in electrical properties. The interface formed between the each layers affected the current path, resulting in reduced electrical performance. However, when the gate bias VG = 10 V was applied for 1500 s, the threshold voltage shift decreased in the stack. The uniformity of the active layer was improved in the stacked active layer by filling the hole formed during pre-baking, resulting in improved device stability. Also, the indium ratio was increased to enhance the mobility from 0.86 to 3.47. These results suggest high mobility and high stability devices can be produced with multistacked active layers.

The Effect of Electrical Stress on the New Top Gate N-type Depletion Mode Polycrystalline Thin Film Transistors Fabricated by Alternating Magnetic Field Enhanced Rapid Thermal Annealing

2008 ◽  
Vol 1066 ◽  
Author(s):  
Won-Kyu Lee ◽  
Sang-Myeon Han ◽  
Sang-Geun Park ◽  
Sung-Hwan Choi ◽  
Joonhoo Choi ◽  
...  
Keyword(s):  
Magnetic Field ◽  
Thin Film ◽  
Thermal Annealing ◽  
Rapid Thermal Annealing ◽  
Thin Film Transistors ◽  
Polycrystalline Silicon ◽  
State Density ◽  
Alternating Magnetic Field ◽  
Threshold Voltage Shift ◽  
Electrical Stress

ABSTRACTWe have fabricated the new top gate depletion mode n-type alternating magnetic field enhanced rapid thermal annealing (AMFERTA) polycrystalline silicon (poly-Si) thin film transistors (TFTs), which show the excellent electrical characteristics and superior stability compared with hydrogenated amorphous silicon (a-Si:H) TFTs and excimer laser crystallized (ELC) low temperature polycrystalline silicon (LTPS) TFTs. The fabricated AMFERTA poly-Si TFTs were not degraded under hot-carrier stress, and highly biased vertical field stress. The considerably large threshold voltage shift (ΔVTH) and trap state density reducing were occurred when the gate bias and drain bias were both large enough. The dominant mechanism of instability in the fabricated depletion mode AMFERTA poly-Si TFTs may be due to carrier induced donor-like defects reduction within the channel layer, especially near the drain junction.

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