scholarly journals Fabrication of Sn@Al2O3 Core-shell Nanoparticles for Stable Nonvolatile Memory Applications

Materials ◽  
2019 ◽  
Vol 12 (19) ◽  
pp. 3111
Author(s):  
Jong-Hwan Yoon

Sn@Al2O3 core-shell nanoparticles (NPs) with narrow spatial distributions were synthesized in silicon dioxide (SiO2). These Sn@Al2O3 core-shell NPs were self-assembled by thermally annealing a stacked structure of SiOx/Al/Sn/Al/SiOx sandwiched between two SiO2 layers at low temperatures. The resultant structure provided a well-defined Sn NP floating gate with a SiO2/Al2O3 dielectric stacked tunneling barrier. Capacitance-voltage (C-V) measurements on a metal-oxide-semiconductor (MOS) capacitor with a Sn@Al2O3 core-shell NP floating gate confirmed an ultra-high charge storage stability, and the multiple trapping of electron at the NPs, as expected from low-k/high-k dielectric stacked tunneling layers and metallic NPs, respectively.

2008 ◽  
Vol 55 (12) ◽  
pp. 3610-3614 ◽  
Author(s):  
Hai Liu ◽  
Wyatt Winkenwerder ◽  
Yueran Liu ◽  
Domingo Ferrer ◽  
Davood Shahrjerdi ◽  
...  

2011 ◽  
Vol 422 ◽  
pp. 139-145
Author(s):  
Wan Yi Huang ◽  
Hong Bing Chen ◽  
Sun Chen ◽  
Shi Jin Ding ◽  
David Wei Zhang

Pd nanocrystals embedded in TiO2film are formed in a self-assembly manner by rapid thermal annealing (RTA) of reactively co-sputtered TiPdO films. The cross-section transmission-electron microscopy (TEM) image and X-ray photoelectron spectra (XPS) reveal that the RTA at 800°C for 15 s results in the formation of Pd nanocrystals with an average size of around 10 nm. Further, the metal-oxide-semiconductor (MOS) capacitor with Pd-nanocrystals-embedded TiO2film sandwiched between Al2O3layers has been fabricated and characterized electrically in comparison with the counterpart without Pd nanocrystals, indicating that the formed Pd nanocrystals are dominant charge storage nodes. The fabricated MOS capacitor with Pd nanocrystals exhibits obvious memory characteristics, demonstrating a C-V hysteresis window of about 8.2 V at the sweeping voltage rang of +/-9 V, a flatband voltage shift of ~2V under a constant voltage stress of +9V for 10ns corresponding to a charge injection speed of 6×1012cm-2μs-1. The underlying mechanisms of the memory characteristics under different C-V sweeps have also been discussed.


2012 ◽  
Vol 27 (1) ◽  
pp. 95-101
Author(s):  
Shi-Bin LIU ◽  
Chun-Ying YANG ◽  
Zhong-Lin ZHANG ◽  
Dong-Hong DUAN ◽  
Xiao-Gang HAO ◽  
...  

2013 ◽  
Vol 20 (28) ◽  
pp. 3488-3499 ◽  
Author(s):  
Yon Jung ◽  
Hwanbum Lee ◽  
Jae Kim ◽  
Eun Koo ◽  
Keun Oh ◽  
...  

2021 ◽  
Vol 330 ◽  
pp. 129364
Author(s):  
Jinhua Wang ◽  
Jiamin Wu ◽  
Yuping Zhang ◽  
Xia Zhou ◽  
Ziwei Hu ◽  
...  

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