scholarly journals A New Multilevel Inverter Topology with Reduced DC Sources

Energies ◽  
2021 ◽  
Vol 14 (15) ◽  
pp. 4709
Author(s):  
Muhyaddin Rawa ◽  
Prem P ◽  
Jagabar Sathik Mohamed Ali ◽  
Marif Daula Siddique ◽  
Saad Mekhilef ◽  
...  
Keyword(s):  
Software Tool ◽  
Multilevel Inverter ◽  
Basic Unit ◽  
Peak Efficiency ◽  
Power Semiconductor ◽  
Power Semiconductor Devices ◽  
Higher Power ◽  
Control Requirement ◽  
The Given ◽  
Inverter Topology

The component count for the multilevel inverter has been a research topic for the last few decades. The higher number of power semiconductor devices and sources leads to a higher power loss with the complex control requirement. A new multilevel inverter topology employing the concept of half-Bridge modules is suggested in this paper. It requires a lower number of dc sources and power components. The inverter is controlled using a fundamental frequency switching scheme. With the basic unit being able to produce 13 level voltage waveforms with three dc voltage sources, higher-level inverter configuration has also been discussed in the paper. The performance of the topology is analyzed in the aspects of circuit parameters and found better when compared to similar topologies proposed in recent literature. The comparison provided in the paper set the benchmark of the proposed topology in terms of lower component requirements. The topology is also optimized with two voltage fixing algorithms for maximizing the number of levels for the given number of IGBTs, drivers and dc sources, and the observations are presented. The efficiency analysis gives the peak efficiency as 98.5%. The simulations were carried out using the PLECS software tool and validated using a prototype rated at 500 W. The results with several test conditions have been reported and discussed in the paper.

A New Asymmetric and Cascaded Switched Diode Multilevel Inverter Topology for Reduced Switches, DC Source and Blocked Voltage on Switches

2019 ◽  
Vol 28 (04) ◽  
pp. 1950064 ◽  
Author(s):  
S. A. Ahamed Ibrahim ◽  
P. Anbalagan ◽  
M. A. Jagabar Sathik
Keyword(s):  
High Power ◽  
Output Voltage ◽  
Multilevel Inverter ◽  
Basic Unit ◽  
Prototype Model ◽  
Multilevel Converter ◽  
Multilevel Converters ◽  
Medium Voltage ◽  
Blocking Voltage ◽  
Inverter Topology

In this paper, a new asymmetric switched diode (ASD) multilevel inverter is presented for medium-voltage and high-power applications. The proposed converter consists of series connection basic unit with full-bridge inverter. In addition to this, a cascaded switched diode (CSD) structure is recommended to generate the higher number of voltage levels. Seven different algorithms are presented to determine the magnitudes of DC sources in CSD topology. To prove the advantages of proposed multilevel converter over recent multilevel converters in terms of blocking voltage, numbers of IGBTs and on-state switches are presented. To show the authority of the proposed multilevel inverter, it is simulated using MATLAB/Simulink and is experimentally tested using prototype model for 13-level inverter. Finally, various output voltage and current waveforms are shown to prove the dynamic behavior of proposed inverter.

scholarly journals Design and Implementation of a Hybrid Single T-Type Double H-Bridge Multilevel Inverter (STDH-MLI) Topology

Energies ◽  
2019 ◽  
Vol 12 (9) ◽  
pp. 1810 ◽  
Author(s):  
Muhyaddin Rawa ◽  
Marif Daula Siddique ◽  
Saad Mekhilef ◽  
Noraisyah Mohamed Shah ◽  
Hussain Bassi ◽  
...  
Keyword(s):  
Output Voltage ◽  
Detailed Comparison ◽  
Multilevel Inverter ◽  
Basic Unit ◽  
Lower Amount ◽  
Level Control ◽  
Voltage Waveform ◽  
High Quality ◽  
Dc Voltage ◽  
Inverter Topology

Multilevel inverters are proficient in achieving a high-quality staircase output voltage waveform with a lower amount of harmonic content. In this paper, a new hybrid multilevel inverter topology based on the T-type and H-bridge module is presented. The proposed topology aims to achieve a higher number of levels utilizing a lower number of switches, direct current (dc) voltage sources, and voltage stresses across different switches. The basic unit of the proposed single T-type and double H-bridge multilevel inverter (STDH-MLI) produces 15 levels at the output using three dc voltage sources. The proposed topology can be extended by connecting a larger number of dc voltage sources in the T-type section. The nearest level control (NLC) switching technique is used to generate gate pulses for switches to achieve a high-quality output voltage waveform. In addition, a simplified way to achieve NLC is also described in the paper. A detailed comparison with other similar topologies is provided to set the benchmark of the proposed topology. Finally, experimental work is carried out to validate the performance of the proposed topology.

scholarly journals Grid tied PV System using modular multilevel inverter

2019 ◽  
Vol 10 (4) ◽  
pp. 2013
Author(s):  
Sujitha N. ◽  
Partha Sarathi Subudhi ◽  
Krithiga S. ◽  
Angalaeswari S. ◽  
Deepa T. ◽  
...  
Keyword(s):  
Electronic Devices ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Photovoltaic System ◽  
Basic Unit ◽  
Pv System ◽  
Unit Structure ◽  
Dc Power ◽  
Ac Power ◽  
Inverter Topology

A grid tied photovoltaic system using modular multilevel inverter topology is proposed in this paper. Basic unit structure of modular multilevel inverter used in this system is capable of converting DC power from PV array to AC power for feeding power to the household loads or utility grid. The proposed modular multilevel inverter structure has lesser power electronic devices compared to the existing multilevel inverter topologies. The proposed system generates a nearly sinusoidal signal and achieves better output profile with low total harmonic distortion. Simulation of the proposed system is carried out in MATLAB/Simulink software and the results are presented.

Hardware Implementation of 3-level Inverter using Microcontroller for Single Phase Induction Motor

2016 ◽  
Vol 5 (2) ◽  
pp. 99
Author(s):  
Veena B.M. ◽  
Parimala S.K.
Keyword(s):  
Induction Motor ◽  
Single Phase ◽  
Hardware Implementation ◽  
Multilevel Inverter ◽  
Voltage Waveform ◽  
Power Semiconductor ◽  
Semiconductor Switches ◽  
Higher Power ◽  
Elementary Concept ◽  
Lower Voltage

<p>The conventional two level inverter has many limitations for high voltage &amp; high power applications. The term multilevel began with the three-level inverter. Subsequently, several multilevel inverter topologies have been developed. However, the elementary concept of a multilevel inverter to achieve higher power is to use a series of power semiconductor switches with several lower voltage dc sources to perform the power conversion by synthesizing a staircase voltage waveform. Output voltage of 3 level inverter consists of 3 levels, which results smoother output. And hence the THD will be reduced. In this paper Simulink of 3 level inverter and the hardware implementation of micro controller based control of multilevel inverter for single phase Induction motor are presented.</p>

scholarly journals Modified asymmetrical 13-level inverter topology with reduce power semiconductor devices

2020 ◽  
Vol 11 (4) ◽  
pp. 2212
Author(s):  
M Saad Arif ◽  
Zeeshan Sarwer ◽  
Shahrin Md Ayob ◽  
Mohd Zaid ◽  
Shahbaz Ahmad
Keyword(s):  
Level Structure ◽  
Harmonic Distortion ◽  
Level Control ◽  
Power Semiconductor ◽  
Power Semiconductor Devices ◽  
Extensive Analysis ◽  
Polarity Reversals ◽  
Strategy Performance ◽  
Detailed Circuit ◽  
Inverter Topology

This paper introduces a modified multilevel inverter topology with asymmetrical dc sources combination. The significant features of the proposed circuit are the reduced number of switches and low total standing voltage (TSV). Proposed topology utilizes ten switches to produce 13 level output with per unit TSVp.u of 5.33. An additional feature of the proposed topology is the inherent negative level generation as there is no requirement of an H-bridge for the polarity reversals. Nearest level control (NLC) technique is used as the modulation strategy. Performance of the proposed topology is validated through extensive analysis using Simulink and PLECS software. Detailed circuit analysis and its power loss, as well as efficiency studies, have been carried out under constant and dynamic load conditions. Results obtained shows that the proposed topology is working well, producing an output of 13-level with total harmonic distortion of 6.36% and inverter efficiency of 98.8%. The topology is extended to n-level structure, and its generalized expressions for different parameters were formulated. The comparison of the generalized structure with other existing topology is carried out, and it is found that the proposed topology outperform other topologies on many parameters.

Residual Voids in Degassing Process of Encapsulation Gel for Power Semiconductor Devices

2014 ◽  
Vol 134 (6) ◽  
pp. 432-433
Author(s):  
Masahiro Sato ◽  
Akiko Kumada ◽  
Kunihiko Hidaka ◽  
Keisuke Yamashiro ◽  
Yuji Hayase ◽  
...  
Keyword(s):  
Semiconductor Devices ◽  
Power Semiconductor ◽  
Power Semiconductor Devices
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