scholarly journals A 2.45 GHz High Efficiency CMOS RF Energy Harvester with Adaptive Path Control

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1107
Author(s):  
Danial Khan ◽  
Muhammad Basim ◽  
Khuram Shehzad ◽  
Qurat Ul Ain ◽  
Deeksha Verma ◽  
...  
Keyword(s):  
Low Power ◽  
High Power ◽  
High Efficiency ◽  
Power Level ◽  
Research Work ◽  
Load Resistance ◽  
Cmos Technology ◽  
Input Power ◽  
Oxide Semiconductor ◽  
Path Control

In this research work, a reconfigurable 2.45-GHz RF-DC converter realized in a 180-nm complementary metal-oxide semiconductor (CMOS) technology is proposed to efficiently harvest electromagnetic energy. The proposed circuit is composed of a low-power path rectifier, a high-power path rectifier, and an adaptive path control (APC) circuit. The APC circuit is made-up of a comparator, two switches, and an inverter. The APC circuit senses the output voltages of the low-power path and the high-power path rectifiers and generates a control signal to automatically switch the proposed circuit between the lower-power path and the high-power path operation depending upon RF input power level. The proposed circuit obtains more than 20% measured power conversion efficiency (PCE) from −6 dBm to 11 dBm input power range with maximum efficiencies of 41% and 45% at 1 and 6 dBm input powers, respectively, for 5 kΩ load resistance. In addition, the proposed circuit shows excellent performance at 900 MHz and 5.8 GHz frequencies.

scholarly journals Simple Adaptive Rectifier with High Efficiency over a Range of 21 dBm Input Power for RF Energy Harvesting Applications

2021 ◽  
pp. 8-15
Author(s):  
Eman M. Abdelhady ◽  
◽  
Hala M. Abdelkader ◽  
Amr A. Al-Awamry
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Breakdown Voltage ◽  
Adaptive Design ◽  
High Efficiency ◽  
Power Level ◽  
Input Power ◽  
Rf Energy Harvesting ◽  
High Input Power ◽  
Rf Energy

This paper presents a novel simple adaptive and efficient rectifier for Radio Frequency (RF) energy harvesting applications. Traditional rectifiers have maximum RF-DC Power Conversion Efficiency (PCE) over a narrow range of RF input power due to diode breakdown voltage restrictions. The proposed adaptive design helps to extend the PCE over a wider range of RF input power at 2.45GHz using a simple design. Two alternative paths arecontrolled depending on the RF input power level. Low input power levels activate the first path connected to a single rectifier; low power levels make the diode operate below its breakdown voltage and therefore avoiding PCE degradation. High input power levels activate the second path dividing it into three rectifiers. This keeps input power at each rectifier at a low power level to avoid exceeding the diode break down voltage. Simulated PCE of this work is kept above 50% over a range of 21.4 dBm input power from -0.8dBm to 20.6dBm.

scholarly journals A low-area high-efficiency video coding inverse transform core using resource and time sharing architecture

2020 ◽  
Vol 2020 (1) ◽  
Author(s):  
Yuan-Ho Chen ◽  
Chieh-Yang Liu
Keyword(s):  
Video Coding ◽  
Large Scale ◽  
High Efficiency ◽  
Vlsi Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Time Sharing ◽  
High Efficiency Video Coding ◽  
Low Area ◽  
Matrix Products

AbstractIn this paper, a very-large-scale integration (VLSI) design that can support high-efficiency video coding inverse discrete cosine transform (IDCT) for multiple transform sizes is proposed. The proposed two-dimensional (2-D) IDCT is implemented at a low area by using a single one-dimensional (1-D) IDCT core with a transpose memory. The proposed 1-D IDCT core decomposes a 32-point transform into 16-, 8-, and 4-point matrix products according to the symmetric property of the transform coefficient. Moreover, we use the shift-and-add unit to share hardware resources between multiple transform dimension matrix products. The 1-D IDCT core can simultaneously calculate the first- and second-dimensional data. The results indicate that the proposed 2-D IDCT core has a throughput rate of 250 MP/s, with only 110 K gate counts when implemented into the Taiwan semiconductor manufacturing (TSMC) 90-nm complementary metal-oxide-semiconductor (CMOS) technology. The results show the proposed circuit has the smallest area supporting the multiple transform sizes.

scholarly journals Low Power Robust Early Output Asynchronous Block Carry Lookahead Adder with Redundant Carry Logic

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 243 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Douglas Maskell ◽  
Nikos Mastorakis
Keyword(s):  
Low Power ◽  
Digital Signal Processor ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
General Purpose ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Power Cycle

Adder is an important datapath unit of a general-purpose microprocessor or a digital signal processor. In the nanoelectronics era, the design of an adder that is modular and which can withstand variations in process, voltage and temperature are of interest. In this context, this article presents a new robust early output asynchronous block carry lookahead adder (BCLA) with redundant carry logic (BCLARC) that has a reduced power-cycle time product (PCTP) and is a low power design. The proposed asynchronous BCLARC is implemented using the delay-insensitive dual-rail code and adheres to the 4-phase return-to-zero (RTZ) and the 4-phase return-to-one (RTO) handshaking. Many existing asynchronous ripple-carry adders (RCAs), carry lookahead adders (CLAs) and carry select adders (CSLAs) were implemented alongside to perform a comparison based on a 32/28 nm complementary metal-oxide-semiconductor (CMOS) technology. The 32-bit addition was considered for an example. For implementation using the delay-insensitive dual-rail code and subject to the 4-phase RTZ handshaking (4-phase RTO handshaking), the proposed BCLARC which is robust and of early output type achieves: (i) 8% (5.7%) reduction in PCTP compared to the optimum RCA, (ii) 14.9% (15.5%) reduction in PCTP compared to the optimum BCLARC, and (iii) 26% (25.5%) reduction in PCTP compared to the optimum CSLA.

scholarly journals Low Power AVLS-TSPC based 2/3 Pre-Scaler

2019 ◽  
Vol 9 (1) ◽  
pp. 6687-6693
Keyword(s):  
Low Power ◽  
High Efficiency ◽  
Supply Voltage ◽  
Low Frequency ◽  
Cmos Technology ◽  
Frequency Signal ◽  
High Frequency Signal ◽  
Power Requirement ◽  
Fast Pace ◽  
Integer Division

The technology has grown at an ultra-fast pace along with the world. Small devices with less power and high efficiency are in demand. As the circuit size gets smaller, the power requirement increases due to a greater number of transistors. A pre-scaler is a circuit which reduces the high frequency signal to a low frequency signal by integer division. A new approach to low power pre-scaler is proposed in this paper, which is an add-on to the conventional pre-scaler circuit. A true single-phase clock (TSPC) circuit reduces the skew problems in the clock and is used to realize latches and flip-flops. The objective of low power is fulfilled by incorporating the Adaptive Voltage Level Source (AVLS) to TSPC based circuit. The proposed AVLS-TSPC based pre-scaler was analyzed for a frequency of 10 MHz with a supply voltage of 1.8 V for both divide by 2 and 3 modes. The proposed pre-scaler consumes considerably lesser power when compared to that of the existing pre-scaler circuit. The circuits are implemented in 180 nm CMOS technology using Cadence Virtuoso and simulated using Cadence Spectre.

Simulations and Modeling of TFET for Low Power Design

2016 ◽  
pp. 640-667 ◽  
Author(s):  
Sunil Kumar ◽  
Balwinder Raj
Keyword(s):  
Low Power ◽  
Semiconductor Industry ◽  
Complementary Metal Oxide Semiconductor ◽  
Low Power Design ◽  
Cmos Technology ◽  
Oxide Semiconductor ◽  
Manufacturing Cost ◽  
Technology Advancement ◽  
Channel Effects ◽  
Tunnel Fets

In Complementary Metal-Oxide-Semiconductor (CMOS) technology, scaling has been a main key for continuous progress in silicon-based semiconductor industry over the past four decades. However, as the technology advancement on nanometer scale regime for the purpose of building ultra-high density integrated electronic computers and extending performance, CMOS devices are facing fundamental problems such as increased leakage currents, large process parameter variations, short channel effects, increase in manufacturing cost, etc. The new technology must be energy efficient, dense, and enable more device function per unit area and time. There are many novel nanoscale semiconductor devices, this book chapter introduces and summarizes progress in the development of the Tunnel Field-Effect Transistors (TFETs) for low power design. Tunnel FETs are interesting devices for ultra-low power applications due to their steep sub-threshold swing (SS) and very low OFF-current. Tunnel FETs avoid the limit 60mv/decade by using quantum-mechanical Band-to-Band Tunneling (BTBT).

Low loss, fully-printed, ferroelectric varactors for high-power impedance matching at low ISM band frequency

2019 ◽  
Vol 11 (7) ◽  
pp. 658-665
Author(s):  
Daniel Kienemund ◽  
Nicole Bohn ◽  
Thomas Fink ◽  
Mike Abrecht ◽  
Walter Bigler ◽  
...  
Keyword(s):  
High Power ◽  
Power Level ◽  
Impedance Matching ◽  
Input Power ◽  
Low Loss ◽  
Band Frequency ◽  
Power Matching ◽  
Metal Insulator Metal ◽  
Ferroelectric Varactors ◽  
Suppression Technique

AbstractLow loss, ferroelectric, fully-printed varactors for high-power matching applications are presented. Piezoelectric-induced acoustic resonances reduce the power handling capabilities of these varactors by lowering the Q-factor at the operational frequency of 13.56 MHz. Here, a quality factor of maximum 142 is achieved with an interference-based acoustic suppression approach utilizing double metal–insulator–metal structures. The varactors show a tunability of maximum 34% at 300 W of input power. At a power level of 1 kW, the acoustic suppression technique greatly reduces the dissipated power by 62% from 37 W of a previous design to 14.2 W. At this power level, the varactors remain tunable with maximum 18.2% and 200 V of biasing voltage.

Design of Low Power Integrated CMOS Potentiometric Biosensor for Direct Electronic Detection of DNA Hybridization

2014 ◽  
Vol 67 (1) ◽  
Author(s):  
Wong How Hwan ◽  
Vinny Lam Siu Fan ◽  
Yusmeeraz Yusof
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Dna Hybridization ◽  
Point Of Care ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Channel Length ◽  
Electrical Signal ◽  
Oxide Semiconductor ◽  
Detection Circuit

The purpose of this research is to design a low power integrated complementary metal oxide semiconductor (CMOS) detection circuit for charge-modulated field-effect transistor (CMFET) and it is used for the detection of deoxyribonucleic acid (DNA) hybridization. With the available CMOS technology, it allows the realization of complete systems which integrate the sensing units and transducing elements in the same device. Point-of-care (POC) testing device is a device that allows anyone to operate anywhere and obtain immediate results. One of the important features of POC device is low power consumption because it is normally battery-operated. The power consumption of the proposed integrated CMOS detection circuit requires only 14.87 mW. The detection circuit will amplify the electrical signal that comes from the CMFET to a specified level in order to improve the recording characteristics of the biosensor. Self-cascode topology was used in the drain follower circuit in order to reduce the channel length modulation effect. The proposed detection circuit was designed with 0.18µm Silterra CMOS fabrication process and simulated under Cadence Simulation Tool. 

scholarly journals Aerosol droplet-size distribution and airborne nicotine portioning in particle and gas phases emitted by electronic cigarettes

2020 ◽  
Vol 10 (1) ◽  
Author(s):  
Hélène Lalo ◽  
Lara Leclerc ◽  
Jérémy Sorin ◽  
Jérémie Pourchez
Keyword(s):  
Particle Size ◽  
Particle Size Distribution ◽  
Low Power ◽  
Size Distribution ◽  
High Power ◽  
Electronic Cigarettes ◽  
Power Level ◽  
Particle Phase ◽  
Experimental Conditions ◽  
Aerosol Droplet

AbstractThe reliable characterization of particle size distribution and nicotine delivery emitted by electronic cigarettes (ECs) is a critical issue in their design. Indeed, a better understanding of how nicotine is delivered as an aerosol with an appropriate aerodynamic size is a necessary step toward obtaining a well-designed nicotine transfer from the respiratory tract to the bloodstream to better satisfy craving and improve smoking cessation rates. To study these two factors, recent models of EC devices and a dedicated vaping machine were used to generate aerosols under various experimental conditions, including varying the EC power level using two different types of atomizers. The aerodynamic particle sizing of the resulting aerosol was performed using a cascade impactor. The nicotine concentration in the refill liquid and the aerosol droplet was quantified by liquid chromatography coupled with a photodiode array. The vaporization process and the physical and chemical properties of the EC aerosol were very similar at 15 watts (W) and 25 W using the low-power atomizer but quite distinct at 50 W using the high-power atomizer, as follows: (1) the mass median aerodynamic diameters ranged from 1.06 to 1.19 µm (µm) for low power and from 2.33 to 2.46 µm for high power; (2) the nicotine concentrations of aerosol droplets were approximately 11 mg per milliliter (mg/mL) for low power and 17 mg/mL for high power; and (3) the aerosol droplet particle phase of the total nicotine mass emitted by EC was 60% for low power and 95% for high power. The results indicate that varying the correlated factors (1) the power level and (2) the design of atomizer (including the type of coil and the value of resistance used) affects the particle-size distribution and the airborne nicotine portioning between the particle phase and the gas phase in equilibrium with the airborne droplets.

scholarly journals Novel Low-Complexity and Low-Power Flip-Flop Design

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 783
Author(s):  
Jin-Fa Lin ◽  
Zheng-Jie Hong ◽  
Chang-Ming Tsai ◽  
Bo-Cheng Wu ◽  
Shao-Wei Yu
Keyword(s):  
Low Power ◽  
Average Power ◽  
Circuit Complexity ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Digital Circuit ◽  
Oxide Semiconductor ◽  
System Level ◽  
Flip Flop ◽  
Chip Area

In this paper, a compact and low-power true single-phase flip-flop (FF) design with fully static operations is presented. The design is developed by using various circuit-reduction schemes and features a hybrid logic style employing both pass transistor logic (PTL) and static complementary metal-oxide semiconductor (CMOS) logic to reduce circuit complexity. These circuit optimization measures pay off in various aspects, including smaller clock-to-Q (CQ) delay, lower average power, lower leakage power, and smaller layout area; and the transistor-count is only 17. Fabricated in TSMC 180 nm CMOS technology, it reduces by over 29% the chip area compared to the conventional transmission gate FF (TGFF). To further show digital circuit/system level advantages, a multi-mode shift register has been realized. Experimental measurement results at 1.8 V/4 MHz show that, compared with the TGFF design, the proposed design saves 64.7% of power consumption while reducing chip area by 26.2%.

P-48: An Oxide-Semiconductor (OS) FET-based Low-Power Level Shifter Combined with OS LSI Technology-based Display-Controller COG for a Low-Power OS Display System

2017 ◽  
Vol 48 (1) ◽  
pp. 1419-1422
Author(s):  
Hiroki Inoue ◽  
Fumika Akasawa ◽  
Marina Hiyama ◽  
Susumu Kawashima ◽  
Koji Kusunoki ◽  
...  
Keyword(s):  
Low Power ◽  
Power Level ◽  
Oxide Semiconductor ◽  
Display System ◽  
Level Shifter
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