scholarly journals High Efficiency Ring-LWE Cryptoprocessor Using Shared Arithmetic Components

Electronics ◽  
2020 ◽  
Vol 9 (7) ◽  
pp. 1075
Author(s):  
Tuy Nguyen Tan ◽  
Tram Thi Bao Nguyen ◽  
Hanho Lee
Keyword(s):  
Great Reduction ◽  
Processing Time ◽  
High Efficiency ◽  
Path Delay ◽  
Hardware Complexity ◽  
Multiple Path ◽  
Novel Approach ◽  
Encryption And Decryption ◽  
Learning With Errors

A high efficiency architecture for ring learning with errors (ring-LWE) cryptoprocessor using shared arithmetic components is presented in this paper. By applying a novel approach for sharing number theoretic transform (NTT) polynomial multiplier and polynomial adder in encryption and decryption operations, the total number of polynomial multipliers and polynomial adders used in the proposed ring-LWE cryptoprocessor are reduced. In addition, the processing time of NTT polynomial multiplier is speeded up by employing multiple-path delay feedback (MDF) architecture and deploying pipelined technique between all stages of NTT processes. As a result, the proposed architecture offers a great reduction in terms of the hardware complexity and computation latency compared with existing works. The implementation result for the proposed ring-LWE cryptoprocessor on Virtex-7 FPGA board using Xilinx VIVADO shows a significant decrease in the number of slices and LUTs compared with previous works. Moreover, the proposed ring-LWE cryptoprocessor offers higher throughput and efficiency than its predecessors.

scholarly journals Efficient-Scheduling Parallel Multiplier-Based Ring-LWE Cryptoprocessors

Electronics ◽  
2019 ◽  
Vol 8 (4) ◽  
pp. 413 ◽  
Author(s):  
Tuy Nguyen Tan ◽  
Hanho Lee
Keyword(s):  
Field Programmable Gate Array ◽  
Path Delay ◽  
Hardware Complexity ◽  
Parallel Multiplier ◽  
Multiplication Operation ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Speed Up ◽  
Learning With Errors ◽  
Single Path

This paper presents a novel architecture for ring learning with errors (LWE) cryptoprocessors using an efficient approach in encryption and decryption operations. By scheduling multipliers to work in parallel, the encryption and decryption time are significantly reduced. In addition, polynomial multiplications are conducted using radix-2 and radix-8 multiple delay feedback (MDF) architecture-based number theoretic transform (NTT) multipliers to speed up the multiplication operation. To reduce the hardware complexity of an NTT multiplier, three bit-reverse operations during the NTT and inverse NTT (INTT) processes are removed. Polynomial additions in the ring-LWE encryption phase are also arranged to work simultaneously to reduce the latency. As a result, the proposed efficient-scheduling parallel multiplier-based ring-LWE cryptoprocessors can achieve higher throughput and efficiency compared with existing architectures. The proposed ring-LWE cryptoprocessors are synthesized and verified using Xilinx VIVADO on a Virtex-7 field programmable gate array (FPGA) board. With security parameters n = 512 and q = 12,289, the proposed cryptoprocessors using radix-2 single-path delay feedback (SDF), radix-2 MDF, and radix-8 MDF multipliers perform encryption in 4.58 μ s, 1.97 μ s, and 0.89 μ s, and decryption in 4.35 μ s, 1.82 μ s, and 0.71 μ s, respectively. A comparison of the obtained throughput and efficiency with those of previous studies proves that the proposed cryptoprocessors achieve a better performance.

scholarly journals Novel Approach Through the Harmonized Sulfur in Disordered Carbon Structure for High-Efficiency Sodium-Ion Exchange

2020 ◽  
Vol 12 (39) ◽  
pp. 43750-43760 ◽  
Author(s):  
Hanvin Kim ◽  
Dae-Yeong Kim ◽  
Shungo Zen ◽  
Jun Kang ◽  
Nozomi Takeuchi
Keyword(s):  
Ion Exchange ◽  
High Efficiency ◽  
Sodium Ion ◽  
Carbon Structure ◽  
Novel Approach ◽  
Disordered Carbon

scholarly journals High Efficiency Generalized Parallel Counters for Look-Up Table Based FPGAs

2015 ◽  
Vol 2015 ◽  
pp. 1-16 ◽  
Author(s):  
Burhan Khurshid ◽  
Roohie Naaz Mir
Keyword(s):  
Power Dissipation ◽  
High Speed ◽  
High Efficiency ◽  
Critical Path ◽  
Fir Filters ◽  
Path Delay ◽  
Look Up Table ◽  
Improved Performance ◽  
Ip Cores ◽  
Low Efficiency

Generalized parallel counters (GPCs) are used in constructing high speed compressor trees. Prior work has focused on utilizing the fast carry chain and mapping the logic onto Look-Up Tables (LUTs). This mapping is not optimal in the sense that the LUT fabric is not fully utilized. This results in low efficiency GPCs. In this work, we present a heuristic that efficiently maps the GPC logic onto the LUT fabric. We have used our heuristic on various GPCs and have achieved an improvement in efficiency ranging from 33% to 100% in most of the cases. Experimental results using Xilinx 5th-, 6th-, and 7th-generation FPGAs and Stratix IV and V devices from Altera show a considerable reduction in resources utilization and dynamic power dissipation, for almost the same critical path delay. We have also implemented GPC-based FIR filters on 7th-generation Xilinx FPGAs using our proposed heuristic and compared their performance against conventional implementations. Implementations based on our heuristic show improved performance. Comparisons are also made against filters based on integrated DSP blocks and inherent IP cores from Xilinx. The results show that the proposed heuristic provides performance that is comparable to the structures based on these specialized resources.

Wi-Fi location fingerprinting using an intelligent checkpoint sequence

2017 ◽  
Vol 11 (3) ◽  
Author(s):  
Günther Retscher ◽  
Hannes Hofer
Keyword(s):  
Success Rate ◽  
Mobile Device ◽  
Processing Time ◽  
Signal Strength ◽  
Reference Points ◽  
Regular Grid ◽  
Correct Order ◽  
Location Fingerprinting ◽  
Novel Approach ◽  
Logical Sequence

AbstractFor Wi-Fi positioning location fingerprinting is very common but has the disadvantage that it is very labour consuming for the establishment of a database (DB) with received signal strength (RSS) scans measured on a large number of known reference points (RPs). To overcome this drawback a novel approach is developed which uses a logical sequence of intelligent checkpoints (iCPs) instead of RPs distributed in a regular grid. The iCPs are the selected RPs which have to be passed along the way for navigation from a start point A to the destination B. They are twofold intelligent because of the fact that they depend on their meaningful selection and because of their logical sequence in their correct order. Thus, always the following iCP is known due to a vector graph allocation in the DB and only a small limited number of iCPs needs to be tested when matching the current RSS scans. This reduces the required processing time significantly. It is proven that the iCP approach achieves a higher success rate than conventional approaches. In average correct matching results of 90.0% were achieved using a joint DB including RSS scans of all employed smartphones. An even higher success rate is achieved if the same mobile device is used in both the training and positioning phase.

scholarly journals A Novel Architecture of Radix-3 Singlepath Delay Feedback (R3SDF) FFT Using MCSLA

2018 ◽  
Vol 10 (1) ◽  
pp. 37
Author(s):  
Periyarselvam K ◽  
Saravanakumar G ◽  
Anand M
Keyword(s):  
Power Consumption ◽  
Orthogonal Frequency Division Multiplexing ◽  
Digital Signal ◽  
Path Delay ◽  
Hardware Complexity ◽  
Large Power ◽  
Fft Processor ◽  
Novel Design ◽  
Multiplexing Systems ◽  
Single Path

Fast Fourier transform (FFT) is widely used in digital signal processing and telecommunications, particularly in orthogonal frequency division multiplexing systems, to overcome the problems associated with orthogonal subcarriers. A new algorithm of radix-3 FFT has been introduced in this work. The DFT of length N can be realized from three DFT sequences; each of length N/3.Radix-3 algorithm reduces the number of multiplications required for realizing DFT.A novel design of Radix-3pipelined Single path Delay Feedback (R3SDF) FFT using MCSLA has been proposed in this paper. First, the pipelined radix-3 SDF FFT method has been designed. It has less area and large power consumption and delay. In order to overcome these problems, modified carry select adder structure is used to perform the adder operation for reducing the power consumption and delay. Finally, the MCSLA is integrated into radix-3 SDF FFT processor. The hardware complexity and execution time for implementing radix-3 FFT algorithm can be reduced than other FFTs.

scholarly journals Optimal Falling Track Design for Twice detonating Fuze of Double event Fuel air Explosive with High Speed

2020 ◽  
Vol 70 (4) ◽  
pp. 366-373
Author(s):  
Congliang Ye ◽  
Qi Zhang
Keyword(s):  
High Speed ◽  
High Efficiency ◽  
Single Point ◽  
Design System ◽  
Motion Trajectory ◽  
Novel Approach ◽  
Scale Experiment ◽  
Set Up ◽  
Point Center ◽  
Double Event

To prevent the initiation failure caused by the uncontrolled fuze and improve the weapon reliability in the high-speed double-event fuel-air explosive (DEFAE) application, it is necessary to study the TDF motion trajectory and set up a twice-detonating fuze (TDF) design system. Hence, a novel approach of realising the fixed single-point center initiation by TDF within the fuel air cloud is proposed. Accordingly, a computational model for the TDF motion state with the nonlinear mechanics analysis is built due to the expensive and difficult full-scale experiment. Moreover, the TDF guidance design system is programmed using MATLAB with the equations of mechanical equilibrium. In addition, by this system, influences of various input parameters on the TDF motion trajectory are studied in detail singly. Conclusively, the result of a certain TDF example indicates that this paper provides an economical idea for the TDF design, and the developed graphical user interface of high-efficiency for the weapon designers to facilitate the high-speed DEFAE missile development.

Sign in / Sign up

Export Citation Format

Share Document