scholarly journals A Sub-Threshold Differential CMOS Schmitt Trigger with Adjustable Hysteresis Based on Body Bias Technique

Electronics ◽  
2020 ◽  
Vol 9 (5) ◽  
pp. 806
Author(s):  
Sara Radfar ◽  
Ali Nejati ◽  
Yasin Bastan ◽  
Parviz Amiri ◽  
Mohammad Hossein Maghami ◽  
...  
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
The Body ◽  
Cmos Process ◽  
Electronic Systems ◽  
Silicon Area ◽  
Hysteresis Width ◽  
Suitable Candidate ◽  
Body Bias

This paper presents a sub-threshold differential CMOS Schmitt trigger with tunable hysteresis, which can be used to enhance the noise immunity of low-power electronic systems. By exploiting the body bias technique to the positive feedback transistors, the hysteresis of the proposed Schmitt trigger is generated, and it can be adjusted by the applied bias voltage to the bulk terminal of the utilized PMOS transistors. The principle of operation and the main formulas of the proposed circuit are discussed. The circuit is designed in a 0.18-μm standard CMOS process with a 0.6 V power supply. Post-layout simulation results show that the hysteresis width of the Schmitt trigger can be adjusted from 45.5 mV to 162 mV where the ratio of the hysteresis width variation to supply voltage is 19.4%. This circuit consumes 10.52 × 7.91 μm2 of silicon area, and its power consumption is only 1.38 µW, which makes it a suitable candidate for low-power applications such as portable electronic, biomedical, and bio-implantable systems.

A Low-Voltage Bulk-Driven Differential CMOS Schmitt Trigger with Tunable Hysteresis

2019 ◽  
Vol 28 (07) ◽  
pp. 1920004 ◽  
Author(s):  
Ali Nejati ◽  
Yasin Bastan ◽  
Parviz Amiri ◽  
Mohammad Hossein Maghami
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Schmitt Trigger ◽  
Noise Removal ◽  
Cmos Process ◽  
Current Feedback ◽  
Silicon Area ◽  
Hysteresis Width ◽  
Common Mode Voltage ◽  
Simulation Results

This paper describes a low-voltage bulk-driven differential CMOS Schmitt trigger with tunable hysteresis for use in noise removal applications. The hysteresis of the proposed Schmitt trigger is designed based on a regenerative current feedback and its width is adjustable by two control voltages. The center of the hysteresis can also be adjusted by either the control voltages or input common-mode voltage. The principle operation of the proposed circuit is discussed, its main formulas are derived and its performance is verified by Cadence post-layout simulations. Designed in the TSMC 0.18[Formula: see text][Formula: see text]m standard CMOS process, the circuit consumes [Formula: see text]m2 of silicon area. Post-layout simulation results indicate that the hysteresis width of the Schmitt trigger can be adjusted from 170 to 270[Formula: see text]mV and the ratio of the hysteresis width variation to supply voltage is 11.11%. Operated with 0.8[Formula: see text]V supply voltage, the power consumption of the circuit ranges from 0.48 to 1.12[Formula: see text]mW.

scholarly journals Low-Power Two-Phase Clocking Adiabatic PUF Circuit

Electronics ◽  
2021 ◽  
Vol 10 (11) ◽  
pp. 1258
Author(s):  
Câncio Monteiro ◽  
Yasuhiro Takahashi
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Process Variations ◽  
The Body ◽  
Cmos Process ◽  
Clock Signal ◽  
Process Technology ◽  
Two Phase ◽  
Ambient Temperatures ◽  
Start Up

Internet of Things (IoT) has enabled battery-powered devices to transmit sensitive data, while presenting high power consumption and security issues. To address these challenges, adiabatic-based physical unclonable functions (PUFs) offer a promising solution for low-power and secure IoT device applications. In this study, we propose a novel low-power two-phase clocking adiabatic PUF. The proposed adiabatic PUF utilizes a trapezoidal power clock signal with a time-ramped voltage to achieve an improved energy efficiency and reliable start-up PUF behavior. Static CMOS logic is employed to produce stable challenge-response pairs (CRPs) in the adiabatic mode. The pull-down network is designed to control the PUF cell to charge and discharge its output nodes with a constant supply current during secure key generation. The body effect of PMOS transistors, ambient temperatures, and CMOS process variations are investigated to examine the uniqueness and reliability of the proposed work. The proposed adiabatic PUF is simulated using 0.18 µm CMOS process technology with a supply voltage of 1.8 V. The uniqueness and reliability of the proposed adiabatic PUF are 49.82% and 99.47%, respectively. In addition, it requires a start-up power of 0.47 µW and consumes an energy of 15.98 fJ/bit/cycle at the reference temperature of 27 °C.

COMPOSITE TRANSISTOR CELL USING DYNAMIC BODY BIAS FOR HIGH GAIN AND LOW-VOLTAGE APPLICATIONS

2014 ◽  
Vol 23 (08) ◽  
pp. 1450108 ◽  
Author(s):  
VANDANA NIRANJAN ◽  
ASHWANI KUMAR ◽  
SHAIL BALA JAIN
Keyword(s):  
Low Power ◽  
Large Scale ◽  
Low Voltage ◽  
Supply Voltage ◽  
High Gain ◽  
Signal Frequency ◽  
Output Impedance ◽  
Self Cascode ◽  
Intrinsic Gain ◽  
Body Bias

In this work, a new composite transistor cell using dynamic body bias technique is proposed. This cell is based on self cascode topology. The key attractive feature of the proposed cell is that body effect is utilized to realize asymmetric threshold voltage self cascode structure. The proposed cell has nearly four times higher output impedance than its conventional version. Dynamic body bias technique increases the intrinsic gain of the proposed cell by 11.17 dB. Analytical formulation for output impedance and intrinsic gain parameters of the proposed cell has been derived using small signal analysis. The proposed cell can operate at low power supply voltage of 1 V and consumes merely 43.1 nW. PSpice simulation results using 180 nm CMOS technology from Taiwan Semiconductor Manufacturing Company (TSMC) are included to prove the unique results. The proposed cell could constitute an efficient analog Very Large Scale Integration (VLSI) cell library in the design of high gain analog integrated circuits and is particularly interesting for biomedical and instrumentation applications requiring low-voltage low-power operation capability where the processing signal frequency is very low.

scholarly journals A 0.3 V Rail-to-Rail Ultra-Low-Power OTA with Improved Bandwidth and Slew Rate

2021 ◽  
Vol 11 (2) ◽  
pp. 19
Author(s):  
Francesco Centurelli ◽  
Riccardo Della Sala ◽  
Pietro Monsurrò ◽  
Giuseppe Scotti ◽  
Alessandro Trifiletti
Keyword(s):  
Low Power ◽  
Low Voltage ◽  
Supply Voltage ◽  
Cmos Process ◽  
Slew Rate ◽  
Large Signal ◽  
Output Stage ◽  
Ultra Low Power ◽  
Input Stage ◽  
Rail To Rail

In this paper, we present a novel operational transconductance amplifier (OTA) topology based on a dual-path body-driven input stage that exploits a body-driven current mirror-active load and targets ultra-low-power (ULP) and ultra-low-voltage (ULV) applications, such as IoT or biomedical devices. The proposed OTA exhibits only one high-impedance node, and can therefore be compensated at the output stage, thus not requiring Miller compensation. The input stage ensures rail-to-rail input common-mode range, whereas the gate-driven output stage ensures both a high open-loop gain and an enhanced slew rate. The proposed amplifier was designed in an STMicroelectronics 130 nm CMOS process with a nominal supply voltage of only 0.3 V, and it achieved very good values for both the small-signal and large-signal Figures of Merit. Extensive PVT (process, supply voltage, and temperature) and mismatch simulations are reported to prove the robustness of the proposed amplifier.

Low-Power and Reference-Less Data and Clock Recovery Circuit for Visible Light Receivers

2018 ◽  
Author(s):  
Ming-Cheng Liu ◽  
Paul C.-P. Chao ◽  
Soh Sze Khiong
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Visible Light ◽  
Low Voltage ◽  
Supply Voltage ◽  
Clock And Data Recovery ◽  
Optical Receiver ◽  
Clock Recovery ◽  
Cmos Process ◽  
Rf Receiver

In this paper a low power all-digital clock and data recovery (ADCDR) with 1Mhz frequency has been proposed. The proposed circuit is designed for optical receiver circuit on the battery-less photovoltaic IoT (Internet of Things) tags. The conventional RF receiver has been replaced by the visible light optical receiver for battery-less IoT tags. With this proposed ADCDR a low voltage, low power consumption & tiny IoT tags can be fabricated. The proposed circuit achieve the maximum bandwidth of 1MHz, which is compatible with the commercial available LED and light sensor. The proposed circuit has been fabricated in TSMC 0.18um 1P6M standard CMOS process. Experimental results show that the power consumption of the optical receiver is approximately 5.58uW with a supply voltage of 1V and the data rate achieves 1Mbit/s. The lock time of the ADCDR is 0.893ms with 3.31ns RMS jitter period.

A 16.4 nW, Sub-1 V, Resistor-Less Voltage Reference with BJT Voltage Divider

2018 ◽  
Vol 27 (13) ◽  
pp. 1850206 ◽  
Author(s):  
Qingshan Yang ◽  
Peiqing Han ◽  
Niansong Mei ◽  
Zhaofeng Zhang
Keyword(s):  
Low Voltage ◽  
Supply Voltage ◽  
Voltage Divider ◽  
Total Power ◽  
Cmos Process ◽  
Operating Voltage ◽  
Voltage Reference ◽  
Ultra Low Power ◽  
Silicon Area ◽  
Total Power Consumption

A 16.4[Formula: see text]nW, sub-1[Formula: see text]V voltage reference for ultra-low power low voltage applications is proposed. This design reduces the operating voltage to 0.8[Formula: see text]V by a BJT voltage divider and decreases the silicon area considerably by eliminating resistors. The PTAT and CTAT are based on SCM structures and a scaled-down [Formula: see text], respectively, to improve the process insensitivity. This work is fabricated in 0.18[Formula: see text][Formula: see text]m CMOS process with a total area of 0.0033[Formula: see text]mm2. Measured results show that it works properly for supply voltage from 0.8[Formula: see text]V to 2[Formula: see text]V. The reference voltage is 467.2[Formula: see text]mV with standard deviation ([Formula: see text]) being 12.2 mV and measured TC at best is 38.7[Formula: see text]ppm/[Formula: see text]C ranging from [Formula: see text]C to 60[Formula: see text]C. The total power consumption is 16.4[Formula: see text]nW under the minimum supply voltage at 27[Formula: see text]C.

scholarly journals Design of Low Power and Low Phase Noise Current Starved Ring Oscillator for RFID Tag EEPROM

2019 ◽  
pp. 19-23
Keyword(s):  
Low Power ◽  
Phase Noise ◽  
Power Dissipation ◽  
Supply Voltage ◽  
Ring Oscillator ◽  
Cmos Process ◽  
Clock Signal ◽  
Voltage Level ◽  
Rfid Tag ◽  
Low Phase Noise

Power dissipation of CMOS IC is a key factor in low power applications especially in RFID tag memories. Generally, tag memories like electrically erasable programmable read-only memory (EEPROM) require an internal clock generator to regulate the internal voltage level properly. In EEPROM, oscillator circuit can generate any periodic clock signal for frequency translation. Among different types of oscillators, a current starved ring oscillator (CSRO) is described in this research due to its very low current biasing source, which in turn restrict the current flows to reduce the overall power dissipation. The designed CSRO is limited to three stages to reduce the power dissipation to meet the specs. The simulated output shows that, the improved CSRO dissipates only 4.9 mW under the power supply voltage (VDD) 1.2 V in Silterra 130 nm CMOS process. Moreover, this designed oscillator has the lowest phase noise -119.38 dBc/Hz compared to other research works. In addition, the designed CSRO is able to reduce the overall chip area, which is only 0.00114 mm2. Therefore, this proposed low power and low phase noise CSRO will be able to regulate the voltage level successfully for low power RFID tag EEPROM.

scholarly journals A 0.3 V PNN Based 10T SRAM with Pulse Control Based Read-Assist and Write Data-Aware Schemes for Low Power Applications

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6591
Author(s):  
Ming-Hwa Sheu ◽  
Chang-Ming Tsai ◽  
Ming-Yan Tsai ◽  
Shih-Chang Hsia ◽  
S. M. Salahuddin Morsalin ◽  
...  
Keyword(s):  
Low Power ◽  
Supply Voltage ◽  
Random Access ◽  
Average Energy ◽  
Cmos Process ◽  
Pulse Control ◽  
Power Performance ◽  
Process Technology ◽  
Low Leakage ◽  
Noise Margin

An innovative and stable PNN based 10-transistor (10T) static random-access memory (SRAM) architecture has been designed for low-power bit-cell operation and sub-threshold voltage applications. The proposed design belongs to the following features: (a) pulse control based read-assist circuit offers a dynamic read decoupling approach for eliminating the read interference; (b) we have utilized the write data-aware techniques to cut off the pull-down path; and (c) additional write current has enhanced the write capability during the operation. The proposed design not only solves the half-selected problems and increases the read static noise margin (RSNM) but also provides low leakage power performance. The designed architecture of 1-Kb SRAM macros (32 rows × 32 columns) has been implemented based on the TSMC-40 nm GP CMOS process technology. At 300 mV supply voltage and 10 MHz operating frequency, the read and write power consumption is 4.15 μW and 3.82 μW, while the average energy consumption is only 0.39 pJ.

scholarly journals A 920-MHz Dual-Mode Receiver with Energy Harvesting for UHF RFID Tag and IoT

Electronics ◽  
2020 ◽  
Vol 9 (6) ◽  
pp. 1042
Author(s):  
Peiqing Han ◽  
Zhaofeng Zhang ◽  
Yajun Xia ◽  
Niansong Mei
Keyword(s):  
Energy Harvesting ◽  
Low Power ◽  
Radio Frequency Identification ◽  
Supply Voltage ◽  
High Sensitivity ◽  
Cmos Process ◽  
Uhf Rfid ◽  
Dual Mode ◽  
Operating Modes ◽  
On Chip

A low-power dual-mode receiver is presented for ultra-high-frequency (UHF) radio frequency identification (RFID) systems. The reconfigurable architecture of the tag is proposed to be compatible with low-power and high-sensitivity operating modes. The read range of RFID system and the lifetime of the tag are increased by photovoltaic, thermoelectric and RF energy-harvesting topology. The receiver is implemented in a 0.18-μm standard CMOS process and occupies an active area of 0.65 mm × 0.7 mm. For low-power mode, the tag is powered by the rectifier and the sensitivity is −18 dBm. For high-sensitivity mode, the maximum PCE of the fully on-chip energy harvester is 46.5% with over 1-μW output power and the sensitivity is −40 dBm with 880 nW power consumption under the supply voltage of 0.8 V.

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