scholarly journals Design of Soft-Switching Hybrid DC-DC Converter with 2-Phase Switched Capacitor and 0.8nH Inductor for Standard CMOS Process

Electronics ◽  
2020 ◽  
Vol 9 (2) ◽  
pp. 372
Author(s):  
Minho Choi ◽  
Deog-Kyoon Jeong
Keyword(s):  
Maximum Load ◽  
Soft Switching ◽  
Voltage Regulator ◽  
Cmos Process ◽  
Switched Capacitor ◽  
Peak Efficiency ◽  
Switching Operation ◽  
Fully Integrated ◽  
Standard Cmos Process ◽  
Adaptive Timing

A soft-switching hybrid DC-DC converter with a 2-phase switched capacitor is proposed for the implementation of a fully-integrated voltage regulator in a 65 nm standard CMOS process. The soft-switching operation is implemented to minimize power loss due to the parasitic capacitance of the flying capacitor. The 2-phase switched capacitor topology keeps the same resonance value for every soft-switching operation, resulting in minimizing the voltage imbalance of the flying capacitor. The proposed adaptive timing generator digitally calibrates the turn-on delay of switches to achieve a complete soft-switching operation. The simulation results show that the proposed soft-switching hybrid DC-DC converter with a 2-phase 2:1 switched capacitor improves the efficiency by 5.1% and achieves 79.5% peak efficiency at a maximum load current of 250 mA.

scholarly journals Design consideration in low dropout voltage regulator for batteryless power management unit

2019 ◽  
Vol 8 (4) ◽  
Author(s):  
Mohamad Khairul bin Mohd Kamel ◽  
Yan Chiew Wong
Keyword(s):  
System Development ◽  
Maximum Load ◽  
Open Loop ◽  
Low Noise ◽  
Green Technology ◽  
Voltage Regulator ◽  
Cmos Process ◽  
Process Technology ◽  
Pass Filter ◽  
Low Pass Filter

Harvesting energy from ambient Radio Frequency (RF) source is a great deal toward batteryless Internet of Thing (IoT) System on Chip (SoC) application as green technology has become a future interest. However, the harvested energy is unregulated thus it is highly susceptible to noise and cannot be used efficiently. Therefore, a dedicated low noise and high Power Supply Ripple Rejection (PSRR) of Low Dropout (LDO) voltage regulator are needed in the later stages of system development to supply the desired load voltage. Detailed analysis of the noise and PSRR of an LDO is not sufficient. This work presents a design of LDO to generate a regulated output voltage of 1.8V from 3.3V input supply targeted for 120mA load application. The performance of LDO is evaluated and analyzed. The PSRR and noise in LDO have been investigated by applying a low-pass filter. The proposed design achieves the design specification through the simulation results by obtaining 90.85dB of open-loop gain, 76.39º of phase margin and 63.46dB of PSRR respectively. The post-layout simulation shows degradation of gain and maximum load current due to parasitic issue. The measurement of maximum load regulation is dropped to 96mA compared 140mA from post-layout. The proposed LDO is designed using 180nm Silterra CMOS process technology.

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