scholarly journals A Design of Hybrid Appliance Local Network (HALN) Communication Architecture

Electronics ◽  
2020 ◽  
Vol 9 (1) ◽  
pp. 170
Author(s):  
Hyoung-Jun Park ◽  
Dongik Lee
Keyword(s):  
Power Consumption ◽  
Service Discovery ◽  
Local Network ◽  
Communication Architecture ◽  
Communication Architectures ◽  
Communication Reliability ◽  
Http Protocol ◽  
Service Discovery Protocol

Recently, appliance networks have been widely adopted in many home applications. Usually, an appliance network requires a server. However, as the number of network users increases, there is not only the problem of costs due to extension of the server and the increase in power consumption, but also the problem that the functions of appliances are restricted when the connection to a server is unavailable. This paper presents a hybrid appliance local network (HALN) communication architecture to tackle the problems with server-based appliance networks. The HALN architecture is designed to remove and/or minimize the utilization of servers by offering the capability of communicating directly with other appliance products. The proposed architecture can also be integrated with existing server-based communication architectures. The HALN architecture is based on the simple service discovery protocol (SSDP) and HTTP protocol (RESTful HTTP server/client architecture) technologies. The effectiveness of HALN is experimentally demonstrated using a smartphone and a set of Linux-based Wi-Fi modems on which the functions that can be provided by typical appliances are implemented. Using the proposed architecture, the communication reliability is also improved by 1.6% as compared with that of an existing server-based communication architecture.

scholarly journals Routing Communication Inside Ad Hoc Drones Network

2021 ◽  
Vol 15 (17) ◽  
pp. 192
Author(s):  
Hamza Zemrane ◽  
Youssef Baddi ◽  
Abderrahim Hasbi
Keyword(s):  
Cellular Network ◽  
Satellite Communication ◽  
Ad Hoc ◽  
Video Conferencing ◽  
Network Communication ◽  
Database Queries ◽  
Communication Architecture ◽  
The World ◽  
Communication Architectures ◽  
Http Protocol

The world knows a constant development of technology applied in different sectors of activities: health, factories, homes, transportation, and others, one of the big axes that take a lot of attention today is the drone’s field. To communicate information a fleet of drones can use different communication architectures: centralized communication architecture, satellite communication architecture, cellular network communication architecture and a specific AdHoc communication architecture called the UAANET drones architecture. In our work we focused specifically on the routing of information inside the UAANET where we analyze and compare the performances of the reactive protocol AODV and the proactive protocol OLSR, when the UAANET use an applications based on the HTTP protocol, the FTP protocol, the database queries, voice application, and video conferencing application.

Secure On-Chip Communication Architecture for Reconfigurable Multi-Core Systems

2016 ◽  
Vol 25 (08) ◽  
pp. 1650089 ◽  
Author(s):  
Ahmed Saeed ◽  
Ali Ahmadinia ◽  
Mike Just
Keyword(s):  
Power Consumption ◽  
Secure Communication ◽  
Functional Verification ◽  
Primary Concern ◽  
Memory Architecture ◽  
Core System ◽  
Communication Architecture ◽  
Data Packets ◽  
Communication Architectures ◽  
On Chip

Security is becoming the primary concern in today’s embedded systems. Network-on-chip (NoC)-based communication architectures have emerged as an alternative to shared bus mechanism in multi-core system-on-chip (SoC) devices and the increasing number and functionality of processing cores have made such systems vulnerable to security attacks. In this paper, a secure communication architecture has been presented by designing an identity and address verification (IAV) security module, which is embedded in each router at the communication level. IAV module verifies the identity and address range to be accessed by incoming and outgoing data packets in an NoC-based multi-core shared memory architecture. Our IAV module is implemented on an FPGA device for functional verification and evaluated in terms of its area and power consumption overhead. For FPGA-based systems, the IAV module can be reconfigured at run-time through partial reconfiguration. In addition, a cycle-accurate simulation is carried out to analyze the performance and total network energy consumption overhead for different network configurations. The proposed IAV module has presented reduced area and power consumption overhead when compared with similar existing solutions.

scholarly journals A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees

VLSI Design ◽  
2007 ◽  
Vol 2007 ◽  
pp. 1-11 ◽  
Author(s):  
Srinivasan Murali ◽  
David Atienza ◽  
Luca Benini ◽  
Giovanni De Micheli
Keyword(s):  
Power Consumption ◽  
Network Performance ◽  
Multipath Routing ◽  
Experimental Studies ◽  
Packet Delivery ◽  
Network Bandwidth ◽  
Routing Strategy ◽  
Communication Architectures ◽  
Multiple Paths ◽  
Single Path

Networks on Chips (NoCs) are required to tackle the increasing delay and poor scalability issues of bus-based communication architectures. Many of today's NoC designs are based on single path routing. By utilizing multiple paths for routing, congestion in the network is reduced significantly, which translates to improved network performance or reduced network bandwidth requirements and power consumption. Multiple paths can also be utilized to achieve spatial redundancy, which helps in achieving tolerance against faults or errors in the NoC. A major problem with multipath routing is that packets can reach the destination in an out-of-order fashion, while many applications require in-order packet delivery. In this work, we present a multipath routing strategy that guarantees in-order packet delivery for NoCs. It is based on the idea of routing packets on partially nonintersecting paths and rebuilding packet order at path reconvergent nodes. We present a design methodology that uses the routing strategy to optimally spread the traffic in the NoC to minimize the network bandwidth needs and power consumption. We also integrate support for tolerance against transient and permanent failures in the NoC links in the methodology by utilizing spatial and temporal redundancy for transporting packets. Our experimental studies show large reduction in network bandwidth requirements (36.86% on average) and power consumption (30.51% on average) compared to single-path systems. The area overhead of the proposed scheme is small (a modest 5% increase in network area). Hence, it is practical to be used in the on-chip domain.

scholarly journals Highly scalable intelligent sensory application and time domain matrix for safety-critical system design

2018 ◽  
Vol 14 (4) ◽  
pp. 155014771774110
Author(s):  
Taikyeong Ted Jeong
Keyword(s):  
Fault Detection ◽  
Detection Algorithm ◽  
Network Interface ◽  
Critical System ◽  
Communication Architecture ◽  
Interface Card ◽  
Safety Critical ◽  
Verification Methods ◽  
Communication Architectures ◽  
And Performance

The designs of highly scalable intelligent sensory application—Ethernet-based communication architectures—are moving toward the integration of a fault recovery and fault-detection algorithm on the automotive industry. In particular, each port on the same network interface card design is required to provide highly scalable and low-latency communication. In this article, we present a study of intelligent sensory application for the Ethernet-based communication architecture and performance of multi-port configuration which is mainly used in safety-enhanced application such as automotive, military, finance, and aerospace, in other words, safety-critical applications. Our contributions and observations on the highly scalable intelligent behavior: (1) proposed network interface card board design scheme and architecture with multi-port configuration are a stable network configuration; (2) timing matrix is defined for fault detection and recovery time; (3) experimental and related verification methods by cyclic redundancy check between client–server and testing platform provide comparable results to each port configurations; and (4) application program interface–level algorithm is defined to make network interface card ready for fault detection.

Runtime Service Discovery for Grid Applications

2009 ◽  
pp. 212-234 ◽  
Author(s):  
James Dooley ◽  
Andrea Zisman ◽  
George Spanoudakis
Keyword(s):  
Social Networks ◽  
Service Discovery ◽  
Large Scale ◽  
Virtual Organisations ◽  
Small World ◽  
Resource Discovery ◽  
Local Network ◽  
Network Node ◽  
Grid Resource ◽  
New Generation

A Virtual Organisation in large-scale distributed systems is a set of individuals and/or institutions with some common purposes or interests that need to share their resources to further their objectives, which is similar to a human community in social networks that consists of people have common interests or goals. Due to the similarity between social networks and Grids, the concepts in social science (e.g. small world phenomenon) can be adopted for the design of new generation Grid systems. This chapter presents a Small World Architecture for Effective Virtual Organisations (SWEVO) for Grid resource discovery in Virtual Organisations, which enables Virtual Organisations working in a more collaborative manner to support decision makers. In SWEVO, Virtual Organisations are connected by a small number of interorganisational links. Not every local network node needs to be connected to remote Virtual Organisations, but every network node can efficiently find connections to specific Virtual Organisations.

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