scholarly journals Benchmarking a Many-Core Neuromorphic Platform With an MPI-Based DNA Sequence Matching Algorithm

Electronics ◽  
2019 ◽  
Vol 8 (11) ◽  
pp. 1342
Author(s):  
Gianvito Urgese ◽  
Francesco Barchi ◽  
Emanuele Parisi ◽  
Evelina Forno ◽  
Andrea Acquaviva ◽  
...  
Keyword(s):  
Dna Sequence ◽  
Parallel Architecture ◽  
General Purpose ◽  
Sequence Matching ◽  
Matching Algorithm ◽  
Computing Platform ◽  
Globally Asynchronous Locally Synchronous ◽  
Efficient Communication ◽  
The Many ◽  
Many Core

SpiNNaker is a neuromorphic globally asynchronous locally synchronous (GALS) multi-core architecture designed for simulating a spiking neural network (SNN) in real-time. Several studies have shown that neuromorphic platforms allow flexible and efficient simulations of SNN by exploiting the efficient communication infrastructure optimised for transmitting small packets across the many cores of the platform. However, the effectiveness of neuromorphic platforms in executing massively parallel general-purpose algorithms, while promising, is still to be explored. In this paper, we present an implementation of a parallel DNA sequence matching algorithm implemented by using the MPI programming paradigm ported to the SpiNNaker platform. In our implementation, all cores available in the board are configured for executing in parallel an optimised version of the Boyer-Moore (BM) algorithm. Exploiting this application, we benchmarked the SpiNNaker platform in terms of scalability and synchronisation latency. Experimental results indicate that the SpiNNaker parallel architecture allows a linear performance increase with the number of used cores and shows better scalability compared to a general-purpose multi-core computing platform.

Stereo Vision VLSI Processor Based on Pixel-Serial and Window-Parallel Architecture

2000 ◽  
Vol 12 (5) ◽  
pp. 521-526
Author(s):  
Masanori Hariyama ◽  
◽  
Michitaka Kameyama
Keyword(s):  
Stereo Vision ◽  
Stereo Matching ◽  
Parallel Architecture ◽  
Window Size ◽  
Input Image ◽  
General Purpose ◽  
Image Size ◽  
Matching Algorithm ◽  
Processing Elements ◽  
General Purpose Processor

This article presents a stereo-matching algorithm to establish reliable correspondence between images by selecting a desirable window size for SAD (Sum of Absolute Differences) computation. In SAD computation, parallelism between pixels in a window changes depending on its window size, while parallelism between windows is predetermined by the input-image size. Based on this consideration, a window-parallel and pixel-serial architecture is proposed to achieve 100% utilization of processing elements. Performance of the VLSI processor is evaluated to be more than 10,000 times higher than that of a general-purpose processor.

scholarly journals RUMD: A general purpose molecular dynamics package optimized to utilize GPU hardware down to a few thousand particles

2017 ◽  
Vol 3 (6) ◽  
Author(s):  
Nicholas Bailey ◽  
Trond Ingebrigtsen ◽  
Jesper Schmidt Hansen ◽  
Arno Veldhorst ◽  
Lasse Bøhling ◽  
...  
Keyword(s):  
Molecular Dynamics ◽  
High Performance ◽  
General Purpose ◽  
Graphical Processing Units ◽  
Performance Benchmarks ◽  
Graphical Processing ◽  
And Performance ◽  
Set Up ◽  
The Many ◽  
Many Core

RUMD is a general purpose, high-performance molecular dynamics (MD) simulation package running on graphical processing units (GPU’s). RUMD addresses the challenge of utilizing the many-core nature of modern GPU hardware when simulating small to medium system sizes (roughly from a few thousand up to hundred thousand particles). It has a performance that is comparable to other GPU-MD codes at large system sizes and substantially better at smaller sizes. RUMD is open-source and consists of a library written in C++ and the CUDA extension to C, an easy-to-use Python interface, and a set of tools for set-up and post-simulation data analysis. The paper describes RUMD’s main features, optimizations and performance benchmarks.

Research on highly parallel embedded control system design and implementation method

Impact ◽  
2019 ◽  
Vol 2019 (10) ◽  
pp. 44-46
Author(s):  
Masato Edahiro ◽  
Masaki Gondo
Keyword(s):  
Computer Architecture ◽  
Intelligent Systems ◽  
Large Scale ◽  
General Purpose ◽  
Heterogeneous Structure ◽  
Single Chip ◽  
Powertrain Control ◽  
Processing Power ◽  
Hardware Description ◽  
Many Core

The pace of technology's advancements is ever-increasing and intelligent systems, such as those found in robots and vehicles, have become larger and more complex. These intelligent systems have a heterogeneous structure, comprising a mixture of modules such as artificial intelligence (AI) and powertrain control modules that facilitate large-scale numerical calculation and real-time periodic processing functions. Information technology expert Professor Masato Edahiro, from the Graduate School of Informatics at the Nagoya University in Japan, explains that concurrent advances in semiconductor research have led to the miniaturisation of semiconductors, allowing a greater number of processors to be mounted on a single chip, increasing potential processing power. 'In addition to general-purpose processors such as CPUs, a mixture of multiple types of accelerators such as GPGPU and FPGA has evolved, producing a more complex and heterogeneous computer architecture,' he says. Edahiro and his partners have been working on the eMBP, a model-based parallelizer (MBP) that offers a mapping system as an efficient way of automatically generating parallel code for multi- and many-core systems. This ensures that once the hardware description is written, eMBP can bridge the gap between software and hardware to ensure that not only is an efficient ecosystem achieved for hardware vendors, but the need for different software vendors to adapt code for their particular platforms is also eliminated.

scholarly journals PageRank Implemented with the MPI Paradigm Running on a Many-Core Neuromorphic Platform

2021 ◽  
Vol 11 (2) ◽  
pp. 25
Author(s):  
Evelina Forno ◽  
Alessandro Salvato ◽  
Enrico Macii ◽  
Gianvito Urgese
Keyword(s):  
Parallel Execution ◽  
Spiking Neural Networks ◽  
Massively Parallel ◽  
Current Version ◽  
Hardware Platform ◽  
Pagerank Algorithm ◽  
Programming Paradigm ◽  
Neuromorphic Hardware ◽  
Efficient Communication ◽  
Many Core

SpiNNaker is a neuromorphic hardware platform, especially designed for the simulation of Spiking Neural Networks (SNNs). To this end, the platform features massively parallel computation and an efficient communication infrastructure based on the transmission of small packets. The effectiveness of SpiNNaker in the parallel execution of the PageRank (PR) algorithm has been tested by the realization of a custom SNN implementation. In this work, we propose a PageRank implementation fully realized with the MPI programming paradigm ported to the SpiNNaker platform. We compare the scalability of the proposed program with the equivalent SNN implementation, and we leverage the characteristics of the PageRank algorithm to benchmark our implementation of MPI on SpiNNaker when faced with massive communication requirements. Experimental results show that the algorithm exhibits favorable scaling for a mid-sized execution context, while highlighting that the performance of MPI-PageRank on SpiNNaker is bounded by memory size and speed limitations on the current version of the hardware.

Design of a Novel Parallel Mechanism for Haptic Device

2021 ◽  
pp. 1-63
Author(s):  
Jin Lixing ◽  
Duan Xingguang ◽  
Li Changsheng ◽  
Shi Qingxin ◽  
Wen Hao ◽  
...  
Keyword(s):  
Parallel Mechanism ◽  
Degrees Of Freedom ◽  
Force Feedback ◽  
Parallel Architecture ◽  
General Purpose ◽  
Haptic Device ◽  
Haptic Devices ◽  
Modeling And Optimization ◽  
Teleoperation Systems

Abstract This paper presents a novel parallel architecture with seven active degrees of freedom (DOFs) for general-purpose haptic devices. The prime features of the proposed mechanism are partial decoupling, large dexterous working area, and fixed actuators. The detailed processes of design, modeling, and optimization are introduced and the performance is simulated. After that, a mechanical prototype is fabricated and tested. Results of the simulations and experiments reveal that the proposed mechanism possesses excellent performances on motion flexibility and force feedback. This paper aims to provide a remarkable solution of the general-purpose haptic device for teleoperation systems with uncertain mission in complex applications.

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