scholarly journals Active EMI Reduction Using Chaotic Modulation in a Buck Converter with Relaxed Output LC Filter

Electronics ◽  
2018 ◽  
Vol 7 (10) ◽  
pp. 254 ◽  
Author(s):  
Van Nguyen ◽  
Hai Huynh ◽  
SoYoung Kim ◽  
Hanjung Song
Keyword(s):  
Electromagnetic Interference ◽  
Power Efficiency ◽  
Pulse Width Modulation ◽  
Buck Converter ◽  
Oxide Semiconductor ◽  
Switching Frequency ◽  
Cmos Process ◽  
Reference Case ◽  
Ramp Generator ◽  
Chaotic Mode

DC-DC buck converters are widely used in portable applications because of their high power efficiency. However, their inherent fast switching releases electromagnetic emissions, making them prominent sources of electromagnetic interference (EMI). This paper proposes a voltage-controlled buck converter that reduces EMI by using a chaotic pulse-width modulation (PWM) technique based on a chaotic triangular ramp generator. The chaotic triangular ramp generator is constructed from a simple on-chip chaotic circuit linked with a symmetrically triangular ramp circuit. The proposed converter can thus operate in the chaotic mode reducing the EMI without requiring any EMI filters. Additionally, using the triangular ramp signal can relax the requirement for a large LC output filter in chaotic mode. The effectiveness of the proposed scheme was experimentally verified with a chaotic triangular ramp generator embedded in a voltage-mode controller buck converter using a 0.18 µm Complementary Metal Oxide Semiconductor (CMOS) process. The measurement results from a prototype showed that the EMI improvement from the proposed scheme is approximately 14.53 dB at the fundamental switching frequency with respect to the standard fixed-frequency PWM reference case.

scholarly journals A PWM/PFM Dual-Mode DC-DC Buck Converter with Load-Dependent Efficiency-Controllable Scheme for Multi-Purpose IoT Applications

Energies ◽  
2021 ◽  
Vol 14 (4) ◽  
pp. 960
Author(s):  
Myeong Woo Kim ◽  
Jae Joon Kim
Keyword(s):  
Power Efficiency ◽  
Buck Converter ◽  
Maximum Efficiency ◽  
Switching Frequency ◽  
Cmos Process ◽  
Dual Mode ◽  
Pulse Frequency Modulation ◽  
Heavy Load ◽  
Iot Applications ◽  
Light Load

This paper presents a dual-mode DC-DC buck converter including a load-dependent, efficiency-controllable scheme to support multi-purpose IoT applications. For light-load applications, a selectable adaptive on-time pulse frequency modulation (PFM) control is proposed to achieve optimum power efficiency by selecting the optimum switching frequency according to the load current, thereby reducing unnecessary switching losses. When the inductor peak current value or converter output voltage ripple are considered in some applications, its on-time can be adjusted further. In heavy-load applications, a conventional pulse width modulation (PWM) control scheme is adopted, and its gate driver is structured to reduce dynamic current, preventing the current from shooting through the power switch. A proposed dual-mode buck converter prototype is fabricated in a 180 nm CMOS process, achieving its measured maximum efficiency of 95.7% and power density of 0.83 W/mm2.

Design of Clock and Ramp Generator Circuit Framework with 0.9V Low Operational Voltage

2013 ◽  
Vol 284-287 ◽  
pp. 2502-2508
Author(s):  
Rong Jong Wai ◽  
Jun Jie Liaw
Keyword(s):  
Threshold Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Clean Energy ◽  
Oxide Semiconductor ◽  
Operational Amplifiers ◽  
Cmos Process ◽  
Clock Frequency ◽  
Ramp Generator ◽  
Generator Circuit

In this study, a new clock and ramp generator circuit framework with a 0.9V low operational voltage is designed for the voltage-mode/current-mode-controlled power management integrated chip of a DC-DC converter. In conventional clock and ramp generator circuit with operational amplifiers, its operational voltage is limited to be over 1.5V because of the problem of a higher threshold voltage in the metal-oxide-semiconductor field-effect transistor (MOSFET). As a result, it can not work well for a pulse-width-modulation DC-DC converter when a below 1V low-voltage single-cell clean-energy power source is applied. This newly-design clock and ramp generator circuit framework without operational amplifiers is investigated to cope with the limitation of the threshold voltage in the MOSFET. Therefore, the corresponding chip size and power consumption can be reduced. Moreover, this circuit still has the functions of adjustable clock frequency and ramp slope. In addition, numerical simulations by the HSPICE software and experimental results by a real chip fabricated in the TSMC 1P6M 0.18µm CMOS process are given to verify the effectiveness of the proposed circuit to produce the clock and ramp waveforms.

scholarly journals A Comprehensive Comparison of EMI Immunity in CMOS Amplifier Topologies

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1181 ◽  
Author(s):  
Simone Becchetti ◽  
Anna Richelli ◽  
Luigi Colalongo ◽  
Zsolt Kovacs-Vajna
Keyword(s):  
Electromagnetic Interference ◽  
Printed Circuit Board ◽  
Complementary Metal Oxide Semiconductor ◽  
Circuit Board ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Fair Comparison ◽  
Comprehensive Comparison ◽  
Folded Cascode ◽  
Cmos Amplifier

This paper provides the results of a comprehensive comparison between complementary metal oxide semiconductor (CMOS) amplifiers with low susceptibility to electromagnetic interference (EMI). They represent the state-of-the-art in low EMI susceptibility design. An exhaustive scenario for EMI pollution has been considered: the injected interference can indeed directly reach the amplifier pins or can be coupled from the printed circuit board (PCB) ground. This is also a key point for evaluating the susceptibility from EMI coupled to the output pin. All of the amplifiers are re-designed in a United Microelectronics Corporation (UMC) 180 nm CMOS process in order to have a fair comparison. The topologies investigated and compared are basically derived from the Miller and the folded cascode ones, which are well-known and widely used by CMOS analog designers.

scholarly journals Multicarrier PWM Strategies for Hybrid Symmetrical Multilevel Inverter with Reduced Switch Count

2020 ◽  
Vol 9 (5) ◽  
pp. 860-866
Keyword(s):  
Electromagnetic Interference ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Total Harmonic Distortion ◽  
Switching Frequency ◽  
Third Harmonic ◽  
Multilevel Inverters ◽  
High Switching Frequency

Multilevel inverters are widely used for high power and high voltage applications. The performance of multilevel inverters are superior to conventional two level inverters in terms of reduced total harmonic distortion, higher dc link voltages, lower electromagnetic interference and increased quality in the output voltage waveform. This paper presents a single phase hybrid eleven level multilevel inverter topology with reduced switch count to compensate the above mentioned disadvantages. This paper also presents various high switching frequency based multi carrier pulse width modulation strategies such as Phase Disposition PWM Strategy (PDPWM), Phase Opposition and Disposition PWM Strategy (PODPWM), Alternate Phase opposition Disposition PWM (APODPWM), Carrier Overlapping PWM (COPWM), Variable frequency carrier PWM (VFPWM), Third Harmonic Injection PWM (TFIPWM) applied to the proposed eleven level multilevel inverter and is analyzed for RL load. FFT analysis is carried out and total harmonic distortion, fundamental output voltage are calculated. Simulation is carried out in MATLAB/SMULINK.

scholarly journals Electromagnetic interference of switching mode power regulator with chaotic frequency modulation

2002 ◽  
Vol 15 (1) ◽  
pp. 111-122
Author(s):  
Hei Wong ◽  
Yan Chan ◽  
Sui Wah
Keyword(s):  
Frequency Modulation ◽  
Electromagnetic Interference ◽  
Noise Level ◽  
Pulse Width Modulation ◽  
Chaotic Signal ◽  
Switching Frequency ◽  
Noise Power ◽  
Frequency Range ◽  
Switched Mode Power Supplies ◽  
Switching Mode

In this work, we propose an improved switching scheme (called chaotic frequency modulation (CFM)) for switched-mode power supplies to suppress the electromagnetic interference (EMI) noise source. The basic principle of CFM is to use a chaotic signal to modulate the switching signal so that the harmonics of noise power is distributed evenly over the whole spectrum instead of concentrated at the switching frequency. When compared with the conventional pulse width modulation (PWM) scheme, significant improvements in both conducted and radiated EMI noise levels were found with the proposed CFM method. For conducted EMI, the peak noise level was reduced by 25 dB_V. For radiated EMI, we found that the noise was found mainly in the frequency range of 30 MHz to 230 MHz and the CFM scheme would help to reduce the peak noise level in this frequency range by 22 dB_V.

Implementation and Design of Voltage-Mode PFM Control Buck Power Converter

2013 ◽  
Vol 860-863 ◽  
pp. 2390-2394
Author(s):  
Min Chin Lee ◽  
Ruey Wun Jan
Keyword(s):  
Supply Voltage ◽  
Pulse Frequency ◽  
Power Converter ◽  
Buck Converter ◽  
Switching Frequency ◽  
Cmos Process ◽  
Pulse Frequency Modulation ◽  
Better Regulation ◽  
Chip Size ◽  
Voltage Feedback

A lower power consumption, smaller output ripple and better regulation buck dcdc converter controlled by voltage feedback and pulse-frequency modulation (PFM) mode is implemented in this paper. The converter operating in discontinuous conduction mode (DCM) is designed and simulated using the TSMC 0.18μm 1P6M CMOS Process. Hspice simulation results show that, the buck converter having chip size with power dissipation about 0.68mW. This chip can operate with input supply voltage from 1.2V to 1.8V, and switching frequency from 249KHz () to 50KHz (), and its output voltage can stable at 1.0V and less than 110mV ripple voltage at maximum loading current 100 mA.

scholarly journals High performance DC/DC buck converter using sliding mode controller

2019 ◽  
Vol 10 (4) ◽  
pp. 1806
Author(s):  
Mustafa Abbas Fadel Al-Qaisi ◽  
Mohanad A. Shehab ◽  
Ammar Al-Gizi ◽  
Mohammed Al-Saadi
Keyword(s):  
Electromagnetic Interference ◽  
High Performance ◽  
Pulse Width Modulation ◽  
Sliding Mode ◽  
Maximum Output Power ◽  
Buck Converter ◽  
System Stability ◽  
Control Technique ◽  
Sliding Mode Controller ◽  
Maximum Output

<span>This paper investigated the performance of the sliding mode control technique for dc/dc converter using frequency response method. The applications of the step down type switching regulator) buck converter (are found in the devices that use batteries as power source like laptop, cell phones, electric vehicle, and recently, it  has also been used in the renewable energy processing, as a maximum output power can be achieved at higher efficiency. In order to optimize the efficiency and for convenient power management, the issues like power on transients, the effect of load variation, Switching and Electromagnetic interference (EMI) losses has to be overcome for which controllers are used. In the proposed method, pulse width modulation (PWM) based on proportional-integral-derivative sliding mode voltage controller (PID SMVC) is designed for a buck converter and the response for appropriate control parameters has been obtained. The system stability has been examined and analyzed from the performance characteristics, which shows clearly that the buck converter controlled by the sliding mode controller has fast dynamic response and it’s very efficient for various applications.</span>

Output Voltage Sampling Circuit for Discontinuous Conduction Mode Flyback Pulse-Width Modulation Controller

2016 ◽  
Vol 25 (11) ◽  
pp. 1650140 ◽  
Author(s):  
Ling-Feng Shi ◽  
Zhen-Bo Shi ◽  
Sen Chen ◽  
Jian-Hui Xun
Keyword(s):  
Pulse Width ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Low Voltage ◽  
Low Cost ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Discharge Time ◽  
Constant Output

Primary-side controlled pulse-width modulation (PWM) flyback converter has been widely used in low-power and low-voltage products for its simple structure and low cost. This paper presents a novel output voltage sampling circuit which considers the influence of the rectifier diode current on the output voltage sampling. The output voltage sampling circuit samples the output voltage at 85% of the secondary inductance discharge time [Formula: see text] of last cycle, which improves the accuracy of the output voltage sampling circuit. Besides, the circuit can also sample the secondary inductance discharge time [Formula: see text]. Finally, a chip has been fabricated in 0.6[Formula: see text][Formula: see text]m complementary metal-oxide semiconductor (CMOS) process, which is used in the presented output voltage sampling circuit in its internal circuit to simple output voltage and achieve constant output voltage.

Performance Analysis of Multilevel Inverter with Reduced Number of Switches

2019 ◽  
Vol 16 (2) ◽  
pp. 422-427
Author(s):  
S. Karthikeyan ◽  
K. Lakshmi ◽  
S. Sivaranjani ◽  
J. Karthika ◽  
T. Nandhakumar
Keyword(s):  
Electromagnetic Interference ◽  
Output Voltage ◽  
Pulse Width Modulation ◽  
Control Method ◽  
Harmonic Distortion ◽  
Multilevel Inverter ◽  
Switching Frequency ◽  
Power Semiconductor ◽  
Multilevel Inverters ◽  
Modulation Control

Multilevel inverters are mainly used in high power and medium voltage applications to reduce the required voltage rating of the power semiconductor switching devices. Nowadays multilevel inverters are also preferred for various applications regardless of the power ratings because they can essentially realize lower harmonics with lower switching frequency and lower electromagnetic interference (EMI). However, it has some disadvantages such as increased number of components, complex Pulse Width Modulation control method, and voltage balancing problem. In this paper a new topology of cascaded multilevel inverter using reduced number of switches is introduced resulting in higher output voltage levels. There era five series connected H-bridges and the DC voltage is given in the ratio n0: n: n3:2n2:10n. The output voltage having 123 levels is obtained (61 positive voltage levels, 61 negative voltage levels and zero voltage levels). Reduced Total Harmonic Distortion (THD) makes them useful for electric vehicle, FACTS and has given option for various power applications. The proposed topology results in reduction of cost and has simplicity of control system. Therefore, the overall cost and complexity are greatly reduced particularly for higher output voltage levels.

Complementary Metal Oxide Semiconductor Amplifier Behaviour Considering Different Points of Electromagnetic Interference Injection

2019 ◽  
Vol 15 (4) ◽  
pp. 361-367 ◽  
Author(s):  
Simone Becchetti ◽  
Anna Richelli ◽  
Luigi Colalongo ◽  
Zsolt M. Kovacs-Vajna
Keyword(s):  
Metal Oxide ◽  
Critical Point ◽  
Electromagnetic Interference ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Fair Comparison ◽  
Folded Cascode ◽  
Cmos Amplifier

In this paper the CMOS amplifier behaviour has been further investigated respect to the previous works in the literature. An exhaustive scenario for the EMI pollution has been considered: the injected interferences can indeed directly reach the amplifier pins or can be coupled from the PCB ground. This is a key point for evaluating also the susceptibility from the EMI coupled to the output pin, which is disclosed as a critical point. The investigated topologies are basically derived from the Miller and the Folded Cascode, which are well-known and widely used by the CMOS analog designers; all of them are re-designed in UMC 180 nm CMOS process in order to have a fair comparison.

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