scholarly journals A Comprehensive Comparison of EMI Immunity in CMOS Amplifier Topologies

Electronics ◽  
2019 ◽  
Vol 8 (10) ◽  
pp. 1181 ◽  
Author(s):  
Simone Becchetti ◽  
Anna Richelli ◽  
Luigi Colalongo ◽  
Zsolt Kovacs-Vajna
Keyword(s):  
Electromagnetic Interference ◽  
Printed Circuit Board ◽  
Complementary Metal Oxide Semiconductor ◽  
Circuit Board ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Fair Comparison ◽  
Comprehensive Comparison ◽  
Folded Cascode ◽  
Cmos Amplifier

This paper provides the results of a comprehensive comparison between complementary metal oxide semiconductor (CMOS) amplifiers with low susceptibility to electromagnetic interference (EMI). They represent the state-of-the-art in low EMI susceptibility design. An exhaustive scenario for EMI pollution has been considered: the injected interference can indeed directly reach the amplifier pins or can be coupled from the printed circuit board (PCB) ground. This is also a key point for evaluating the susceptibility from EMI coupled to the output pin. All of the amplifiers are re-designed in a United Microelectronics Corporation (UMC) 180 nm CMOS process in order to have a fair comparison. The topologies investigated and compared are basically derived from the Miller and the folded cascode ones, which are well-known and widely used by CMOS analog designers.

Complementary Metal Oxide Semiconductor Amplifier Behaviour Considering Different Points of Electromagnetic Interference Injection

2019 ◽  
Vol 15 (4) ◽  
pp. 361-367 ◽  
Author(s):  
Simone Becchetti ◽  
Anna Richelli ◽  
Luigi Colalongo ◽  
Zsolt M. Kovacs-Vajna
Keyword(s):  
Metal Oxide ◽  
Critical Point ◽  
Electromagnetic Interference ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Fair Comparison ◽  
Folded Cascode ◽  
Cmos Amplifier

In this paper the CMOS amplifier behaviour has been further investigated respect to the previous works in the literature. An exhaustive scenario for the EMI pollution has been considered: the injected interferences can indeed directly reach the amplifier pins or can be coupled from the PCB ground. This is a key point for evaluating also the susceptibility from the EMI coupled to the output pin, which is disclosed as a critical point. The investigated topologies are basically derived from the Miller and the Folded Cascode, which are well-known and widely used by the CMOS analog designers; all of them are re-designed in UMC 180 nm CMOS process in order to have a fair comparison.

A Technique to Determine the Designable Inductance Value(s) in Wide-Band CMOS-Amplifier System Employing Shunt-Peaking

2015 ◽  
Vol 24 (08) ◽  
pp. 1550119
Author(s):  
R. Raut ◽  
G. Gibson
Keyword(s):  
Transfer Function ◽  
Design Procedure ◽  
Complementary Metal Oxide Semiconductor ◽  
Wide Band ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Bandwidth Extension ◽  
Constant Frequency ◽  
Common Gate ◽  
Cmos Amplifier

This paper presents a technique towards obtaining an estimate of the value of inductor(s) to expand the bandwidth of operation in a complementary metal-oxide semiconductor (CMOS) amplifier system which exploits shunt peaking principle. The basic principle is placement of the zeros of the transfer function in an interleaved manner relative to the uncompensated RC time-constant frequency (TCF) and the band-edge frequency (BEF) (i.e., product of the poles) of the transfer function. Application of the analytical results has been demonstrated for (i) a common-gate (CG) amplifier stage in a 0.18-μm CMOS process and (ii) an inter-stage inductor coupling network which serves as an interface between two amplifier stages. MATLAB simulation has been used to obtain the range of design inductance values. The TSMC 180-nm CMOS process has been used in Cadence CAD environment to validate the theoretical predictions. The inductors laid out have been modeled using the ASITIC program to obtain more realistic results. The proposed technique provides a bandwidth extension of the CMOS common-gate amplifier from 6.68 GHz to 10.4 GHz with 1 dB peaking using only a 1.85-nH inductor. For the inter-stage coupling network, the suggested design procedure leads to a bandwidth extension ratio (BWER) exceeding three, with less than 3-dB ripple.

Coherent J-Band radiating arrays based on ×27 CMOS activemultiplier chips

2019 ◽  
Vol 11 (08) ◽  
pp. 747-754
Author(s):  
Roman Klimovich ◽  
Samuel Jameson ◽  
Eran Socher
Keyword(s):  
Printed Circuit Board ◽  
Complementary Metal Oxide Semiconductor ◽  
Cmos Technology ◽  
Circuit Board ◽  
Oxide Semiconductor ◽  
Power Dividers ◽  
Radiated Power ◽  
Ring Antenna ◽  
On Chip ◽  
Practical Factors

AbstractThis paper presents a hybrid design of 1 × 2 and 1 × 4 arrays operating in 0.277–0.292 THz on 65 nm Complementary metal–oxide–semiconductor (CMOS) technology. Each of the chips has an X-band input with 3 ×3 multiplier stages and connected at the output to an on-chip ring antenna. A wideband microstrip Wilkinson four-way and two-way power dividers have been developed on a multilayer printed circuit board to feed the array elements with proper radio frequency and direct current inputs. Demonstrating improvements in effective isotropically radiated power and in total radiated power compared to a single CMOS element, the hybrid integration approach proves effective in implementing coherent THz transmitter arrays. Theoretical and practical factors that reduce the radiated power compared with ideal arrays are also discussed.

scholarly journals 20–25 Gbit/s low-power inductor-less single-chip optical receiver and transmitter frontend in 28 nm digital CMOS

2017 ◽  
Vol 9 (8) ◽  
pp. 1667-1677 ◽  
Author(s):  
László Szilágyi ◽  
Guido Belfiore ◽  
Ronny Henker ◽  
Frank Ellinger
Keyword(s):  
Laser Diode ◽  
Printed Circuit Board ◽  
Optical Measurements ◽  
Circuit Board ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Single Chip ◽  
Chip Area ◽  
Limiting Amplifier ◽  
28 Nm

The design of an analog frontend including a receiver amplifier (RX) and laser diode driver (LDD) for optical communication system is described. The RX consists of a transimpedance amplifier, a limiting amplifier, and an output buffer (BUF). An offset compensation and common-mode control circuit is designed using switched-capacitor technique to save chip area, provides continuous reduction of the offset in the RX. Active-peaking methods are used to enhance the bandwidth and gain. The very low gate-oxide breakdown voltage of transistors in deep sub-micron technologies is overcome in the LDD by implementing a topology which has the amplifier placed in a floating well. It comprises a level shifter, a pre-amplifier, and the driver stage. The single-chip frontend, fabricated in a 28 nm bulk-digital complementary metal–oxide–semiconductor (CMOS) process has a total active area of 0.003 mm2, is among the smallest optical frontends. Without the BUF, which consumes 8 mW from a separate supply, the RX power consumption is 21 mW, while the LDD consumes 32 mW. Small-signal gain and bandwidth are measured. A photo diode and laser diode are bonded to the chip on a test-printed circuit board. Electro-optical measurements show an error-free detection with a bit error rate of 10−12at 20 Gbit/s of the RX at and a 25 Gbit/s transmission of the LDD.

scholarly journals Phase Change Metasurfaces by Continuous or Quasi-Continuous Atoms for Active Optoelectronic Integration

Materials ◽  
2021 ◽  
Vol 14 (5) ◽  
pp. 1272
Author(s):  
Zhihua Fan ◽  
Qinling Deng ◽  
Xiaoyu Ma ◽  
Shaolin Zhou
Keyword(s):  
Phase Change ◽  
Phase Change Materials ◽  
Complementary Metal Oxide Semiconductor ◽  
Photonic Devices ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Nanophotonic Devices ◽  
Optoelectronic Integration ◽  
Hybrid Devices ◽  
Micro Electromechanical System

In recent decades, metasurfaces have emerged as an exotic and appealing group of nanophotonic devices for versatile wave regulation with deep subwavelength thickness facilitating compact integration. However, the ability to dynamically control the wave–matter interaction with external stimulus is highly desirable especially in such scenarios as integrated photonics and optoelectronics, since their performance in amplitude and phase control settle down once manufactured. Currently, available routes to construct active photonic devices include micro-electromechanical system (MEMS), semiconductors, liquid crystal, and phase change materials (PCMs)-integrated hybrid devices, etc. For the sake of compact integration and good compatibility with the mainstream complementary metal oxide semiconductor (CMOS) process for nanofabrication and device integration, the PCMs-based scheme stands out as a viable and promising candidate. Therefore, this review focuses on recent progresses on phase change metasurfaces with dynamic wave control (amplitude and phase or wavefront), and especially outlines those with continuous or quasi-continuous atoms in favor of optoelectronic integration.

scholarly journals Novel Heat-Mitigating Chip-on-Probe for Brain Stimulation Behavior Experiments

Sensors ◽  
2020 ◽  
Vol 20 (24) ◽  
pp. 7334
Author(s):  
Seongwoog Oh ◽  
Jungsuek Oh
Keyword(s):  
Brain Stimulation ◽  
Heat Sink ◽  
Transmission Loss ◽  
Maximum Output Power ◽  
Circuit Board ◽  
Oxide Semiconductor ◽  
Normal Operation ◽  
Cmos Process ◽  
Maximum Output ◽  
The Brain

This paper proposes a novel design for a chip-on-probe with the aim of overcoming the heat dissipation effect during brain stimulations using modulated microwave signals. The temperature of the stimulus chip during normal operation is generally 40 °C–60 °C, which is sufficient to cause unintended temperature effects during stimulation. This effect is particularly fatal in brain stimulation applications that require repeated stimulation. This paper proposes, for the first time, a topology that vertically separates the stimulus chip generating the stimulus signal and the probe delivering the signal into the brain to suppress the heat transfer while simultaneously minimizing the radio frequency (RF) transmission loss. As the proposed chip-on-probe should be attached to the head of a small animal, an auxiliary board with a heat sink was carefully designed considering the weight that does not affect the behavior experiment. When the transition structures are properly designed, a heat sink can be mounted to maximize the cooling effect, reducing the temperature by more than 13 °C in a simulation when the heat generated by the chip is transferred to the brain, while the transition from the chip to the probe experiences a loss of 1.2 dB. Finally, the effectiveness of the proposed design is demonstrated by fabricating a chip with the 0.28 μm silicon-on-insulator (SOI) complementary metal–oxide–semiconductor (CMOS) process and a probe with a RT6010 printed-circuit board (PCB), showing a temperature reduction of 49.8 °C with a maximum output power of 11 dBm. In the proposed chip-on-probe device, the temperature formed in the area in contact with the brain is measured at 31.1 °C.

scholarly journals Universal Filter Based on Compact CMOS Structure of VDDDA

Sensors ◽  
2021 ◽  
Vol 21 (5) ◽  
pp. 1683
Author(s):  
Winai Jaikla ◽  
Fabian Khateb ◽  
Tomasz Kulej ◽  
Koson Pitaksuttayaprot
Keyword(s):  
Metal Oxide ◽  
Dynamic Range ◽  
Complementary Metal Oxide Semiconductor ◽  
Metal Oxide Semiconductor ◽  
Experimental Results ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Voltage Gain ◽  
Universal Filter ◽  
Mos Transistor

This paper proposes the simulated and experimental results of a universal filter using the voltage differencing differential difference amplifier (VDDDA). Unlike the previous complementary metal oxide semiconductor (CMOS) structures of VDDDA that is present in the literature, the present one is compact and simple, owing to the employment of the multiple-input metal oxide semiconductor (MOS) transistor technique. The presented filter employs two VDDDAs, one resistor and two grounded capacitors, and it offers low-pass: LP, band-pass: BP, band-reject: BR, high-pass: HP and all-pass: AP responses with a unity passband voltage gain. The proposed universal voltage mode filter has high input impedances and low output impedance. The natural frequency and bandwidth are orthogonally controlled by using separated transconductance without affecting the passband voltage gain. For a BP filter, the root mean square (RMS) of the equivalent output noise is 46 µV, and the third intermodulation distortion (IMD3) is −49.5 dB for an input signal with a peak-to peak of 600 mV, which results in a dynamic range (DR) of 73.2 dB. The filter was designed and simulated in the Cadence environment using a 0.18-µm CMOS process from Taiwan semiconductor manufacturing company (TSMC). In addition, the experimental results were obtained by using the available commercial components LM13700 and AD830. The simulation results are in agreement with the experimental one that confirmed the advantages of the filter.

Millimeter-wave dual-mode and dual-band switchable Gilbert up-conversion mixer in 65-nm CMOS process

2021 ◽  
pp. 1-5
Author(s):  
Fang Zhu ◽  
Guo Qing Luo
Keyword(s):  
Millimeter Wave ◽  
Complementary Metal Oxide Semiconductor ◽  
Local Oscillator ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Dual Band ◽  
Cmos Process ◽  
Pumping Power ◽  
Dual Mode ◽  
Dc Power

Abstract In this paper, a millimeter-wave (MMW) dual-mode and dual-band switchable Gilbert up-conversion mixer in a commercial 65-nm complementary metal oxide semiconductor (CMOS) process is presented. By simply changing the bias, the proposed CMOS Gilbert up-conversion mixer can be switched between subharmonic and fundamental operation modes for MMW dual-band applications. With a low local oscillator pumping power of 3 dBm and low dc power consumption of 6 mW, the proposed CMOS Gilbert up-conversion mixer exhibits a measured conversion gain of −0.5 ± 1.5 dB from 37 to 50 GHz and 2.5 ± 1.5 dB from 17.5 to 32 GHz for the subharmonic and fundamental modes, respectively.

scholarly journals Performance Comparison of Carry-Lookahead and Carry-Select Adders Based on Accurate and Approximate Additions

Electronics ◽  
2018 ◽  
Vol 7 (12) ◽  
pp. 369 ◽  
Author(s):  
Padmanabhan Balasubramanian ◽  
Nikos Mastorakis
Keyword(s):  
High Speed ◽  
Digital Signal ◽  
Complementary Metal Oxide Semiconductor ◽  
Performance Comparison ◽  
Oxide Semiconductor ◽  
Cmos Process ◽  
Least Significant Bit ◽  
Design Metrics ◽  
Ripple Carry Adder ◽  
Speed Performance

Addition is a fundamental operation in microprocessing and digital signal processing hardware, which is physically realized using an adder. The carry-lookahead adder (CLA) and the carry-select adder (CSLA) are two popular high-speed, low-power adder architectures. The speed performance of a CLA architecture can be improved by adopting a hybrid CLA architecture which employs a small-size ripple-carry adder (RCA) to replace a sub-CLA in the least significant bit positions. On the other hand, the power dissipation of a CSLA employing full adders and 2:1 multiplexers can be reduced by utilizing binary-to-excess-1 code (BEC) converters. In the literature, the designs of many CLAs and CSLAs were described separately. It would be useful to have a direct comparison of their performances based on the design metrics. Hence, we implemented homogeneous and hybrid CLAs, and CSLAs with and without the BEC converters by considering 32-bit accurate and approximate additions to facilitate a comparison. For the gate-level implementations, we considered a 32/28 nm complementary metal-oxide-semiconductor (CMOS) process targeting a typical-case process–voltage–temperature (PVT) specification. The results show that the hybrid CLA/RCA architecture is preferable among the CLA and CSLA architectures from the speed and power perspectives to perform accurate and approximate additions.

Review: Static and Dynamic Analysis Methods for Multi-Branch Biasing Circuits

2018 ◽  
Vol 27 (13) ◽  
pp. 1830008
Author(s):  
Jin Wu ◽  
Pengfei Dai ◽  
Jie Peng ◽  
Lixia Zheng ◽  
Weifeng Sun
Keyword(s):  
Feedback Loop ◽  
Supply Voltage ◽  
Complementary Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Critical Parameters ◽  
Cmos Process ◽  
Stable Equilibrium Point ◽  
Static And Dynamic Analysis ◽  
Text Structures ◽  
Different Types

The fundamental theories and primary structures for the multi-branch self-biasing circuits are reviewed in this paper. First, the [Formula: see text]/[Formula: see text] and [Formula: see text]/[Formula: see text] structures illustrating the static current definition mechanism are presented, including the conditions of starting up and entering into a stable equilibrium point. Then, the AC method based on the loop gain evaluation is utilized to analyze different types of circuits. On this basis, the laws which can couple the branches of self-biasing circuits to construct a suitable close feedback loop are summarized. By adopting Taiwan Semiconductor Manufacturing Company (TSMC)’s 0.18[Formula: see text][Formula: see text]m complementary metal–oxide–semiconductor (CMOS) process with 1.8[Formula: see text][Formula: see text] supply voltage, nearly all the circuits mentioned in the paper are simulated in the same branch current condition, which is close to the corresponding calculated results. Therefore, the methods summarized in this paper can be utilized for distinguishing, constructing, and optimizing critical parameters for various structures of the self-biasing circuits.

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