scholarly journals Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1800
Author(s):  
Wieslaw Kuzmicz
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Silicon On Insulator ◽  
Operational Amplifiers ◽  
Back Gate ◽  
Fully Depleted ◽  
Linearization Technique ◽  
Mos Devices ◽  
Soi Technology

Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used to improve the linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22 nm FD-SOI technology illustrate this technique, as well as its advantages and limitations.

scholarly journals Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

2021 ◽  
Author(s):  
Wieslaw Kuzmicz
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Operational Amplifiers ◽  
Back Gate ◽  
Linearization Technique ◽  
Mos Devices ◽  
Soi Technology

Negative feedback to the back gate of MOS devices available in FD-SOI technologies can be used to improve linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22nm FD-SOI technology illustrate this technique, its advantages and limitations.

Planar fully depleted SOI technology: The convergence of high performance and low power towards multimedia mobile applications

2012 ◽  
Author(s):  
Bertrand Pelloux-Prayer ◽  
Milovan Blagojevic ◽  
Olivier Thomas ◽  
Amara Amara ◽  
Andrei Vladimirescu ◽  
...  
Keyword(s):  
Low Power ◽  
Mobile Applications ◽  
High Performance ◽  
Fully Depleted ◽  
Soi Technology

Back-gate induced random telegraph signal noise in fully-depleted silicon-on-insulator nMOSFETs

1993 ◽  
Vol 36 (11) ◽  
pp. 1593-1596 ◽  
Author(s):  
E. Simoen ◽  
U. Magnusson ◽  
J. Vermeiren ◽  
C. Claeys
Keyword(s):  
Silicon On Insulator ◽  
Back Gate ◽  
Random Telegraph Signal ◽  
Fully Depleted ◽  
Signal Noise

Towards High-Voltage MOSFETs in Ultrathin FDSOI

2016 ◽  
Vol 25 (01n02) ◽  
pp. 1640005 ◽  
Author(s):  
Antoine Litty ◽  
Sylvie Ortolland ◽  
Dominique Golanski ◽  
Christian Dutto ◽  
Alexandres Dartigues ◽  
...  
Keyword(s):  
High Voltage ◽  
Low Voltage ◽  
Ground Plane ◽  
Silicon Film ◽  
Silicon On Insulator ◽  
Drift Region ◽  
Back Gate ◽  
Fully Depleted ◽  
Buried Oxide ◽  
Core Technology

High-Voltage MOSFETs are essential devices for complementing and extending the domains of application of any core technology including low-power, low-voltage CMOS. In this paper, we propose and describe advanced Extended-Drain MOSFETs, designed, processed and characterized in ultrathin body and buried oxide Fully Depleted Silicon on Insulator technology (UTBB-FDSOI). These transistors have been implemented in two technology nodes (28 nm and 14 nm) with different silicon film and buried oxide thicknesses (TSi < 10nm and TBOX ≤ 25nm). Our innovative concept of Dual Ground Plane (DGP) provides RESURF-like effect (reduced surface field) and offers additional flexibility for HVMOS integration directly in the ultrathin film of the FDSOI wafer. In this configuration, the primary back-gate controls the threshold voltage (VTH) to ensure performance and low leakage current. The second back-gate, located underneath the drift region, acts as a field plate enabling the improvement of the ON resistance (RON) and breakdown voltage (BV). The trade-off RON.S versus BV is investigated as a function of doping level, length and thickness of the drift region. We report promising results and discuss further developments for successful integration of high-voltage MOSFETs in ultrathin CMOS FDSOI technology.

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