Performance Analysis of Modified Source and Tunnel Diode Body Contact Based Fully-Depleted Silicon-on-Insulator MOSFET for Low Power Digital Applications

2017 ◽  
Vol 12 (1) ◽  
pp. 59-66 ◽  
Author(s):  
Vimal Kumar Mishra ◽  
R. K. Chauhan
Keyword(s):  
Performance Analysis ◽  
Low Power ◽  
Tunnel Diode ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
Body Contact

A Tunnel Diode Body Contact SOI MOSFET For Low Power Digital Application

2015 ◽  
Vol 5 (3) ◽  
pp. 35-38
Author(s):  
Nitu Rao ◽  
◽  
VimalKumar Mishra ◽  
R. K. Chauhan ◽  
◽  
...  
Keyword(s):  
Low Power ◽  
Tunnel Diode ◽  
Body Contact ◽  
Soi Mosfet

scholarly journals Linearization Technique of Low Power Opamps in CMOS FD-SOI Technologies

Electronics ◽  
2021 ◽  
Vol 10 (15) ◽  
pp. 1800
Author(s):  
Wieslaw Kuzmicz
Keyword(s):  
Low Power ◽  
Negative Feedback ◽  
Silicon On Insulator ◽  
Operational Amplifiers ◽  
Back Gate ◽  
Fully Depleted ◽  
Linearization Technique ◽  
Mos Devices ◽  
Soi Technology

Negative feedback applied to the back gate of MOS devices available in FD-SOI (fully depleted silicon on insulator) CMOS technologies can be used to improve the linearity of operational amplifiers. Two operational amplifiers designed and fabricated in a 22 nm FD-SOI technology illustrate this technique, as well as its advantages and limitations.

scholarly journals Performance Analysis of Fully-Depleted Silicon-On-Insulator (SOI) G 4 -FET and Gate-All-Around (GAA) MOSFETs

IJIREEICE ◽  
2019 ◽  
Vol 7 (3) ◽  
pp. 1-5
Author(s):  
Md. Rakibul Alam ◽  
Md. Rais Uddin Mollah ◽  
Md. Ferdous Khan
Keyword(s):  
Performance Analysis ◽  
Silicon On Insulator ◽  
Fully Depleted

Low Power 28 nm Fully Depleted Silicon on Insulator 2.45 GHz Phase Locked Loop

2014 ◽  
Vol 10 (1) ◽  
pp. 149-162 ◽  
Author(s):  
Alexandre Fonseca ◽  
Emeric de Foucauld ◽  
Philippe Lorenzini ◽  
Gilles Jacquemod
Keyword(s):  
Low Power ◽  
Phase Locked Loop ◽  
Silicon On Insulator ◽  
Fully Depleted ◽  
28 Nm
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