scholarly journals Embbedded System-on-Chip 3D Localization and Mapping—eSoC-SLAM

Electronics ◽  
2021 ◽  
Vol 10 (12) ◽  
pp. 1378
Author(s):  
Eduardo A. Gerlein ◽  
Gabriel Díaz-Guevara ◽  
Henry Carrillo ◽  
Carlos Parra ◽  
Enrique Gonzalez
Keyword(s):  
Embedded System ◽  
System On Chip ◽  
Embedded Memory ◽  
3D Localization ◽  
Localization And Mapping ◽  
Speed Up ◽  
On Chip ◽  
3D Lidar ◽  
Dual Core ◽  
Computer Board

This paper discusses a novel embedded system-on-chip 3D localization and mapping (eSoC-LAM) implementation, that followed a co-design approach with the primary aim of being deployed in a small system on a programmable chip (SoPC), the Intel’s (a.k.a Altera) Cyclone V 5CSEMA5F31C6N, available in the Terasic’s board DE1-SoC. This computer board incorporates an 800 MHz Dual-core ARM Cortex-A9 and a Cyclone V FPGA with 85k programmable logic elements and 4450 Kbits of embedded memory running at 50 MHz. We report experiments of the eSoC-LAM implementation using a Robosense’s 3D LiDAR RS-16 sensor in a Robotis’ TurtleBot2 differential robot, both controlled by a Terasic’s board DE1-SoC. This paper presents a comprehensive description of the designed architecture, design constraints, resource optimization, HPS-FPGA exchange of information, and co-design results. The eSoC-LAM implementation reached an average speed-up of 6.5× when compared with a version of the algorithm running in a the hard processor system of the Cyclone V device, and a performance of nearly 32 fps, while keeping high map accuracy.

Multiprocessor transport surveillance video system based on "system on chip" technology

2020 ◽  
Author(s):  
Ш.С. Фахми ◽  
Н.В. Шаталова ◽  
В.В. Вислогузов ◽  
Е.В. Костикова
Keyword(s):  
System On Chip ◽  
Reference Points ◽  
Surveillance Video ◽  
Video Information ◽  
Chip Technology ◽  
Intelligent Video Surveillance System ◽  
Speed Up ◽  
Algorithmic Analysis ◽  
Computational Procedures ◽  
On Chip

В данной работе предлагаются математический аппарат и архитектура многопроцессорной транспортной системы на кристалле (МПТСнК). Выполнена программно-аппаратная реализация интеллектуальной системы видеонаблюдения на базе технологии «система на кристалле» и с использованием аппаратного ускорителя известного метода формирования опорных векторов. Архитектура включает в себя сложно-функциональные блоки анализа видеоинформации на базе параллельных алгоритмов нахождения опорных точек изображений и множества элементарных процессоров для выполнения сложных вычислительных процедур алгоритмов анализа с использованием средств проектирования на базе реконфигурируемой системы на кристалле, позволяющей оценить количество аппаратных ресурсов. Предлагаемая архитектура МПТСнК позволяет ускорить обработку и анализ видеоинформации при решении задач обнаружения и распознавания чрезвычайных ситуаций и подозрительных поведений. In this paper, we propose the mathematical apparatus and architecture of a multiprocessor transport system on a chip (MPTSoC). Software and hardware implementation of an intelligent video surveillance system based on the "system on chip" technology and using a hardware accelerator of the well-known method of forming reference vectors. The architecture includes complex functional blocks for analyzing video information based on parallel algorithms for finding image reference points and a set of elementary processors for performing complex computational procedures for algorithmic analysis. using design tools based on a reconfigurable system on chip that allows you to estimate the amount of hardware resources. The proposed MPTSoC architecture makes it possible to speed up the processing and analysis of video information when solving problems of detecting and recognizing emergencies and suspicious behaviors

A Novel Design of Software System on Chip for Embedded System

2016 ◽  
Vol 86 (2-3) ◽  
pp. 135-147 ◽  
Author(s):  
Wei Hu ◽  
Hong Guo ◽  
Hongna Geng ◽  
Kai Zhang ◽  
Jun Liu ◽  
...  
Keyword(s):  
Embedded System ◽  
System On Chip ◽  
Software System ◽  
On Chip ◽  
Novel Design

A Novel Operating System on Chip with Information Security Support for Embedded System

2009 ◽  
Vol 4 (10) ◽  
Author(s):  
Wei Hu ◽  
Tianzhou Chen ◽  
Qingsong Shi ◽  
Gang Wang ◽  
Nan Zhang ◽  
...  
Keyword(s):  
Operating System ◽  
Information Security ◽  
Embedded System ◽  
System On Chip ◽  
On Chip

scholarly journals Hardware-software partitioning using three-level hybrid algorithm for system-on-chip platform

2021 ◽  
Vol 10 (1) ◽  
pp. 466-473
Author(s):  
Tiong Reng Xian ◽  
Zaini Abdul Halim ◽  
Ching Chia Leong ◽  
Tan Jiunn Gim
Keyword(s):  
Embedded System ◽  
Hybrid Algorithm ◽  
High Capacity ◽  
Minimum Cost ◽  
System On Chip ◽  
Swarm Optimization ◽  
Low Diversity ◽  
Field Programmable ◽  
On Chip ◽  
Software Partitioning

This study discusses hardware-software partitioning, which is useful for system-on-chip (SoC) applications. Hardware-software partitioning attempts to obtain the lowest execution time by combining a hardware processor system and a field programmable gate array on the SoC platform in embedded system applications. A three-level hybrid algorithm called GAGAPSO is proposed in this study. The algorithm consists of two successive genetic algorithms (GAs) and one particle swarm optimization (PSO). The drawbacks of these two algorithms are GA has low convergence speed and PSO has premature convergence because of low diversity. These algorithms are combined in this study to achieve high-capacity global convergence and enhanced search efficiency. In this study, three algorithms are developed, namely, GA, GAPSO and GAGAPSO using MATLAB. These algorithms are evaluated on the basis of the number of nodes and the minimum cost that can be achieved. The number of nodes varies from 10 to 1000 nodes. The minimum cost and the number of iterations to achieve the minimum cost are recorded. Results show that GAGAPSO can converge faster than GA and GAPSO. Furthermore, GAGAPSO can achieve the lowest cost for all nodes. 

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