scholarly journals Research on EDAC Schemes for Memory in Space Applications

Electronics ◽  
2021 ◽  
Vol 10 (5) ◽  
pp. 533
Author(s):  
Mengfu Chen ◽  
Chenguang Guo ◽  
Lei Chen ◽  
Wenjie Li ◽  
Fan Zhang ◽  
...  
Keyword(s):  
Error Detection ◽  
Block Codes ◽  
Low Earth Orbit ◽  
Space Applications ◽  
Linear Block Codes ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
Detection Capabilities ◽  
Modular Redundancy ◽  
Time Overhead

Memory used for storing the configuration bitstream of field programmable gate array in space applications often encounters single event upset problems, which may disrupt the integrity of data in memory and lead to unpredictable failures. For commercial memories used in low Earth orbit (LEO), single-bit errors and double-byte errors account for a large proportion. Meanwhile, error detection and correction (EDAC) schemes, e.g., triple modular redundancy, linear block codes, memory scrubbing, and the combination of these schemes, are very popular in LEO missions. To further these works, a novel EDAC scheme with cascaded “Bose–Chaudhuri–Hocquenghem and cyclic redundancy check” codes and a proper scrubbing method is presented in this paper. The performance of the proposed design is measured and compared with state-of-the-art EDAC schemes in terms of hardware overhead, time overhead and error correction and detection capabilities. It is concluded that the proposed EDAC scheme is better suited for memory in space applications.

scholarly journals A One-Cycle Correction Error-Resilient Flip-Flop for Variation-Tolerant Designs on an FPGA

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 633
Author(s):  
Dam Minh Tung ◽  
Nguyen Van Toan ◽  
Jeong-Gun Lee
Keyword(s):  
Integrated Circuits ◽  
Error Detection ◽  
Error Resilience ◽  
Cycle Performance ◽  
Timing Error ◽  
Worst Case ◽  
Flip Flop ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
Performance Penalty

Timing error resilience (TER) is one of the most promising approaches for eliminating design margins that are required due to process, voltage, and temperature (PVT) variations. However, traditional TER circuits have been designed typically on an application-specific integrated circuits (ASIC) where customized circuits and metastability detector designs at a transistor level are possible. On the other hand, it is difficult to implement those designs on a field-programmable gate array (FPGA) due to its predefined LUT structure and irregular wiring. In this paper, we propose an error detection and correction flip-flop (EDACFF) on an FPGA chip, where the metastability issue can be resolved by imposing proper timing constraints on the circuit structures. The proposed EDACFF exploits a transition detector for detecting a timing error along with a data correction latch for correcting the error with one-cycle performance penalty. Our proposed EDACFF is implemented in a 3-bit counter circuit employing a 5-stage pipeline on a Spartan-6 FPGA device (the XFC6SLX45) to verify the functional and timing behavior. The measurement results show that the proposed design obtains 32% less power consumption and 42% higher performance compared to a traditional worst-case design.

scholarly journals FPGA implementation of RGB image encryption and decryption using DNA cryptography

2018 ◽  
Vol 7 (2.8) ◽  
pp. 397 ◽  
Author(s):  
Fazal Noorbasha ◽  
K Suresh
Keyword(s):  
Image Encryption ◽  
Error Detection ◽  
Hamming Code ◽  
Error Detection And Correction ◽  
Dna Cryptography ◽  
Encryption And Decryption ◽  
Field Programmable ◽  
Pixel Image ◽  
Side Error ◽  
Rgb Image

The rapid growth in digitization transmission of information in the form of RGB image. During the process transmission of the image in a channel, some data may be degraded due to noise. At receiver side error in data has to be detected and corrected. Hamming code is one of the popular techniques for error detection and correction. In this paper new algorithm proposed for encryption and decryption of RGB image with DNA cryptography and hamming code for secure transmission, and correction. this algorithm first encodes data to hamming code and encrypted to DNA code. Two-bit error detection and correction for each pixel of the image can be performed.DNA code improves security and use of the Hamming code for error detection and correction. For the image of size 256*256 pixel image, it corrects up to 2*256*256 bits in RGB image. The RGB image encryption and decryption design using Verilog and implemented using FPGA (Field Programmable Gate Array).

Linear block codes for error detection (Corresp.)

1983 ◽  
Vol 29 (1) ◽  
pp. 131-136 ◽  
Author(s):  
T. Kasami ◽  
T. Klove ◽  
Shu Lin
Keyword(s):  
Error Detection ◽  
Block Codes ◽  
Linear Block Codes ◽  
Linear Block

scholarly journals Reduction of Power Consumption using Joint Low Power Code with Crosstalk Avoidance Code in Case of Crosstalk and Random Burst Errors

2018 ◽  
Vol 7 (3.12) ◽  
pp. 62 ◽  
Author(s):  
Ashok Kumar.K ◽  
Dananjayan. P
Keyword(s):  
Power Consumption ◽  
Low Power ◽  
Error Detection ◽  
High Reliability ◽  
Communication Link ◽  
Noise Sources ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
On Chip ◽  
Crosstalk Avoidance

When technology is scaling down, reliability and power issues are arise in the intercommunication of System on Chip (SoC). The intercommunication links are suffers with various noise sources like crosstalk, temperature variation and voltage deflection which lead to communication link failure. To get reliable system, the strong error detection and correction codes are required. In this proposed work, Crosstalk avoidance code detects and corrects of one bit error, two bit error and some of three bit errors. The Hybrid Automatic Re-transmission Request is also used when the CAC detects the burst error of three. Apart from this, the Low Power Codes are used to get low power consumption using Bus Invert (BI) technique in proposed work. The LPC code reduces the power consumption of interconnection wires using reducing switching activity. The performance of proposed work evaluated in Xilinx 14.7 in Vertex-6 Field Programmable Gated Array (FPGA) device. The proposed work is calculated of power consumption of codec module and interconnection wire, delay of CAC and LPC code and link swing voltage. This work provides 11.7% improvement in power consumption and presents high reliability than JTEC. The energy dissipation of wires in the proposed work is decreased 23.5% than un-coded schemes.  

scholarly journals FPGA-Based Reliable Fault Secure Design for Protection against Single and Multiple Soft Errors

Electronics ◽  
2020 ◽  
Vol 9 (12) ◽  
pp. 2064
Author(s):  
Manar N. Shaker ◽  
Ahmed Hussien ◽  
Gehad I. Alkady ◽  
Hassanein H. Amer ◽  
Ihab Adly
Keyword(s):  
Error Detection ◽  
System Reliability ◽  
Fault Tolerant ◽  
Dynamic Partial Reconfiguration ◽  
Access Port ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Modular Redundancy ◽  
Internal Configuration

Field programmable gate arrays (FPGAs) are increasingly used in industry (e.g., biomedical, space, and automotive industries). FPGAs are subjected to single, as well as multiple event upsets (SEUs and MEUs), due to the continuous shrinking of transistor dimensions. These upsets inevitably decrease system lifetime. Fault-tolerant techniques are often used to mitigate these problems. In this research, penta and hexa modular redundancy, as well as dynamic partial reconfiguration (DPR), are used to increase system reliability. We show, depending on the relative rates of the SEUs and MEUs, that penta modular redundancy has a higher reliability than hexa modular redundancy, which is a counter-intuitive result in some cases since increasing redundancy is expected to increase reliability. Focusing on penta modular redundancy, an error detection and recovery mechanism (voter) is designed. This mechanism uses the internal configuration access port (ICAP) and its associated controller, as well as DPR to mitigate SEUs and MEUs. Then, it is implemented on Xilinx Vivado tools targeting the Kintex7 7k410tfbg676 device. Finally, we show how to render this design fault secure in the event that SEUs or MEUs affect the voter itself. This fault secure voter either produces the correct output or gives an indication that the output is incorrect.

scholarly journals A BLOCK COPROCESSOR FOR USER DATA RATE IMPROVEMENTS TO GPRS CODING SCHEME 4

2007 ◽  
Vol 16 (04) ◽  
pp. 541-551 ◽  
Author(s):  
R. SIMON SHERRATT ◽  
KAI ZHANG ◽  
OWEN J. WILKES
Keyword(s):  
Error Detection ◽  
Data Rate ◽  
Mobile Internet ◽  
Full Duplex ◽  
Coding Scheme ◽  
Coding Schemes ◽  
Data Rates ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
User Data

The general packet radio service (GPRS) has been developed to allow packet data to be transported efficiently over an existing circuit-switched radio network, such as GSM. The main application of GPRS are in transporting Internet protocol (IP) datagrams from web servers (for telemetry or for mobile Internet browsers). Four GPRS baseband coding schemes are defined to offer a trade-off in requested data rates versus propagation channel conditions. However, data rates in the order of > 100 kbits/s are only achievable if the simplest coding scheme is used (CS-4) which offers little error detection and correction (EDC) (requiring excellent SNR) and the receiver hardware is capable of full duplex which is not currently available in the consumer market. A simple EDC scheme to improve the GPRS block error rate (BLER) performance is presented, particularly for CS-4, however gains in other coding schemes are seen. For every GPRS radio block that is corrected by the EDC scheme, the block does not need to be retransmitted releasing bandwidth in the channel and improving the user's application data rate. As GPRS requires intensive processing in the baseband, a viable field programmable gate array (FPGA) solution is presented in this paper.

FPGA Implementation of an Error Detection and Correction Algorithm in Mode S-Based ADS-B System

2011 ◽  
Vol 403-408 ◽  
pp. 1839-1844
Author(s):  
Jian Hong Zhou ◽  
Chao Zhang ◽  
Xiao Bin Liu
Keyword(s):  
Error Detection ◽  
Data Transmission ◽  
Signal Transmission ◽  
Transmission Error ◽  
Correction Algorithm ◽  
Description Language ◽  
Error Detection And Correction ◽  
Field Programmable ◽  
Hardware Description ◽  
Correct Data

“ADS-B Messages” transmitted on 1090MHz are the Mode S Extended Squitters. When a Mode A/C fruit interferes with a mode S Extended Squitter, some of ADS-B signals may be received in error. These errors need to be corrected by some correction methods. To solve this problem, an error detection and correction algorithm using cyclic redundancy check (CRC) based on bit and confidence declaration is proposed in this paper. Then, the proposed algorithm using the Verilog hardware description language is verified by MODELSIM joint ISE simulation and realized on Field Programmable Gate Array (FPGA) based on ADS-B system. The results show that the algorithm can effective detect and correct data transmission error, which effective advances the reliability of the signal transmission for ADS-B system.

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