scholarly journals M3-AC: A Multi-Mode Multithread SoC FPGA Based Acoustic Camera

Electronics ◽  
2021 ◽  
Vol 10 (3) ◽  
pp. 317
Author(s):  
Jurgen Vandendriessche ◽  
Bruno da Silva ◽  
Lancelot Lhoest ◽  
An Braeken ◽  
Abdellah Touhafi
Keyword(s):  
Real Time ◽  
Hard Core ◽  
Wireless Sensor ◽  
Sound Sources ◽  
Real Time System ◽  
Acoustic Images ◽  
Field Programmable ◽  
Industrial Monitoring ◽  
On Chip ◽  
Multi Mode

Acoustic cameras allow the visualization of sound sources using microphone arrays and beamforming techniques. The required computational power increases with the number of microphones in the array, the acoustic images resolution, and in particular, when targeting real-time. Such a constraint limits the use of acoustic cameras in many wireless sensor network applications (surveillance, industrial monitoring, etc.). In this paper, we propose a multi-mode System-on-Chip (SoC) Field-Programmable Gate Arrays (FPGA) architecture capable to satisfy the high computational demand while providing wireless communication for remote control and monitoring. This architecture produces real-time acoustic images of 240 × 180 resolution scalable to 640 × 480 by exploiting the multithreading capabilities of the hard-core processor. Furthermore, timing cost for different operational modes and for different resolutions are investigated to maintain a real time system under Wireless Sensor Networks constraints.

Fifty years of Electronic Hardware Implementations of First and Higher Order Neural Networks

2010 ◽  
pp. 269-285 ◽  
Author(s):  
David R. Selviah ◽  
Janti Shawash
Keyword(s):  
Neural Networks ◽  
Real Time ◽  
High Speed ◽  
Higher Order ◽  
Low Latency ◽  
Real Time Control ◽  
Practical Applications ◽  
Field Programmable ◽  
On Chip ◽  
Electronic Hardware

This chapter celebrates 50 years of first and higher order neural network (HONN) implementations in terms of the physical layout and structure of electronic hardware, which offers high speed, low latency, compact, low cost, low power, mass produced systems. Low latency is essential for practical applications in real time control for which software implementations running on CPUs are too slow. The literature review chapter traces the chronological development of electronic neural networks (ENN) discussing selected papers in detail from analog electronic hardware, through probabilistic RAM, generalizing RAM, custom silicon Very Large Scale Integrated (VLSI) circuit, Neuromorphic chips, pulse stream interconnected neurons to Application Specific Integrated circuits (ASICs) and Zero Instruction Set Chips (ZISCs). Reconfigurable Field Programmable Gate Arrays (FPGAs) are given particular attention as the most recent generation incorporate Digital Signal Processing (DSP) units to provide full System on Chip (SoC) capability offering the possibility of real-time, on-line and on-chip learning.

scholarly journals New Mathblocks-Based Feistel-Like Ciphers for Creating Clone-Resistant FPGA Devices

Cryptography ◽  
2019 ◽  
Vol 3 (4) ◽  
pp. 28 ◽  
Author(s):  
Saleh Mulhem ◽  
Wael Adi
Keyword(s):  
Hard Core ◽  
Major Elements ◽  
Physical Unclonable Functions ◽  
Mapping Functions ◽  
The Public ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Near Future

The Secret Unknown Cipher (SUC) concept was introduced a decade ago as a promising technique for creating pure digital clone-resistant electronic units as alternatives to the traditional non-consistent Physical Unclonable Functions (PUFs). In this work, a very special unconventional cipher design is presented. The design uses hard-core FPGA (Field Programmable Gate Arrays) -Mathblocks available in modern system-on-chip (SoC) FPGAs. Such Mathblocks are often not completely used in many FPGA applications; therefore, it seems wise to make use of such dead (unused) modules to fabricate usable physical security functions for free. Standard cipher designs usually avoid deploying multipliers in the cipher mapping functions due to their high complexity. The main target of this work is to design large cipher classes (e.g., cipher class size >2600) by mainly deploying the FPGA specific mathematical cores. The proposed cipher designs are novel hardware-oriented and new in the public literature, using fully new unusual mapping functions. If a random unknown selection of one cipher out of 2600 ciphers is self-configured in a device, then a Secret Unknown Cipher module is created within a device, making it physically hard to clone. We consider the cipher module for free (for zero cost) if the major elements in the cipher module are making use of unused reanimated Mathblocks. Such ciphers are usable in many future mass products for protecting vehicular units against cloning and modeling attacks. The required self-reconfigurable devices for that concept are not available now; however, they are expected to emerge in the near future.

scholarly journals An Autonomous Path Controller in a System on Chip for Shrimp Robot

Electronics ◽  
2020 ◽  
Vol 9 (3) ◽  
pp. 441 ◽  
Author(s):  
Sergio Barrios-dV ◽  
Michel Lopez-Franco ◽  
Jorge D. Rios ◽  
Nancy Arana-Daniel ◽  
Carlos Lopez-Franco ◽  
...  
Keyword(s):  
Path Planning ◽  
Real Time ◽  
Trajectory Tracking ◽  
Neural Control ◽  
Tracking System ◽  
Kinematic Model ◽  
System On Chip ◽  
Optimal Controller ◽  
Real Time System ◽  
On Chip

This paper presents a path planning and trajectory tracking system for a BlueBotics Shrimp III®, which is an articulate mobile robot for rough terrain navigation. The system includes a decentralized neural inverse optimal controller, an inverse kinematic model, and a path-planning algorithm. The motor control is obtained based on a discrete-time recurrent high order neural network trained with an extended Kalman filter, and an inverse optimal controller designed without solving the Hamilton Jacobi Bellman equation. To operate the whole system in a real-time application, a Xilinx Zynq® System on Chip (SoC) is used. This implementation allows for a good performance and fast calculations in real-time, in a way that the robot can explore and navigate autonomously in unstructured environments. Therefore, this paper presents the design and implementation of a real-time system for robot navigation that integrates, in a Xilinx Zynq® System on Chip, algorithms of neural control, image processing, path planning, and inverse kinematics and trajectory tracking.

Real-time audio signal processing using system-on-chip field programmable gate arrays

2019 ◽  
Vol 146 (4) ◽  
pp. 2879-2879
Author(s):  
Ross K. Snider ◽  
Trevor Vannoy ◽  
James Eaton ◽  
Matthew Blunt ◽  
E. Bailey Galacci ◽  
...  
Keyword(s):  
Signal Processing ◽  
Real Time ◽  
Audio Signal ◽  
Field Programmable Gate Arrays ◽  
System On Chip ◽  
Audio Signal Processing ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip

scholarly journals Dual-Mode FPGA-Based Triple-TDC With Real-Time Calibration and a Triple Modular Redundancy Scheme

Electronics ◽  
2020 ◽  
Vol 9 (4) ◽  
pp. 607
Author(s):  
Yuan-Ho Chen
Keyword(s):  
Real Time ◽  
Single Mode ◽  
Triple Modular Redundancy ◽  
Mode Operation ◽  
Differential Nonlinearity ◽  
Time Calibration ◽  
Integral Nonlinearity ◽  
Field Programmable ◽  
Modular Redundancy ◽  
Multi Mode

This paper proposes a triple time-to-digital converter (TDC) for a field-programmable gate array (FPGA) platform with dual operation modes. First, the proposed triple-TDC employs the real-time calibration circuit followed by the traditional tapped delay line architecture to improve the environmental effect for the application of multiple TDCs. Second, the triple modular redundancy scheme is used to deal with the uncertainty in the FPGA device for improving the linearity for the application of a single TDC. The proposed triple-TDC is implemented in a Xilinx Virtex-5 FPGA platform and has a time resolution of 40 ps root mean square for multi-mode operation. Moreover, the ranges of differential nonlinearity and integral nonlinearity can be improved by 56 % and 37 % , respectively, for single-mode operation.

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