scholarly journals Effect of the Conductor Positioning on Low-Power Current Transformers: Inputs for the Next IEC 61869-10

Electricity ◽  
2021 ◽  
Vol 2 (1) ◽  
pp. 1-12
Author(s):  
Alessandro Mingotti ◽  
Lorenzo Peretto ◽  
Roberto Tinarelli
Keyword(s):  
Low Power ◽  
Distribution Network ◽  
Technical Aspect ◽  
Current Transformers ◽  
Correct Usage ◽  
The Future ◽  
Future Version ◽  
Instrument Transformers

Low-power instrument transformers (LPITs) are spreading among the distribution network thanks to their features (e.g., compactness, lightness, enhanced bandwidth, etc.). It is then a fundamental to guide users and manufacturers to a correct usage and manufacturing of the LPITs. Technical committees, which are in charge of writing dedicated standards, often tackle such a task. Focusing on the current type of LPITs, the low-power current transformers (LPCTs), the associated standard is the IEC 61869-10, which is going to be improved in 2021. To this purpose, the work aims at providing new inputs for the future version of such a standard. In particular, the focus is pointed towards the effects of the conductor positioning on the window-type LPCT accuracy. Literature and gained experience in the field are the two pillars that have been used to refine the outcomes of the work, which are provided in terms of suggestions for each technical aspect, as discussed in the standard, related to LPCTs.

Less Power, Greater Conflict

2018 ◽  
Vol 49 (1) ◽  
pp. 47-62 ◽  
Author(s):  
Petra C. Schmid
Keyword(s):  
Low Power ◽  
High Power ◽  
Goal Pursuit ◽  
Goal Conflict ◽  
Personal Goals ◽  
Multiple Goals ◽  
Objective Performance ◽  
The Future ◽  
The Way

Abstract. Power facilitates goal pursuit, but how does power affect the way people respond to conflict between their multiple goals? Our results showed that higher trait power was associated with reduced experience of conflict in scenarios describing multiple goals (Study 1) and between personal goals (Study 2). Moreover, manipulated low power increased individuals’ experience of goal conflict relative to high power and a control condition (Studies 3 and 4), with the consequence that they planned to invest less into the pursuit of their goals in the future. With its focus on multiple goals and individuals’ experiences during goal pursuit rather than objective performance, the present research uses new angles to examine power effects on goal pursuit.

scholarly journals Effect of Step Gate Work Function on InGaAs p-TFET for Low Power Switching Applications

Nanomaterials ◽  
2021 ◽  
Vol 11 (12) ◽  
pp. 3166
Author(s):  
Sayed Md Tariful Azam ◽  
Abu Saleh Md Bakibillah ◽  
Md Tanvir Hasan ◽  
Md Abdus Samad Kamal
Keyword(s):  
Low Power ◽  
Work Function ◽  
Potential Candidate ◽  
Gate Electrodes ◽  
The Future ◽  
Work Function Difference ◽  
High Transconductance ◽  
Dual Material ◽  
Gate Work Function ◽  
Function Difference

In this study, we theoretically investigated the effect of step gate work function on the InGaAs p-TFET device, which is formed by dual material gate (DMG). We analyzed the performance parameters of the device for low power digital and analog applications based on the gate work function difference (∆ϕS-D) of the source (ϕS) and drain (ϕD) side gate electrodes. In particular, the work function of the drain (ϕD) side gate electrodes was varied with respect to the high work function of the source side gate electrode (Pt, ϕS = 5.65 eV) to produce the step gate work function. It was found that the device performance varies with the variation of gate work function difference (∆ϕS-D) due to a change in the electric field distribution, which also changes the carrier (hole) distribution of the device. We achieved low subthreshold slope (SS) and off-state current (Ioff) of 30.89 mV/dec and 0.39 pA/µm, respectively, as well as low power dissipation, when the gate work function difference (∆ϕS-D = 1.02 eV) was high. Therefore, the device can be a potential candidate for the future low power digital applications. On the other hand, high transconductance (gm), high cut-off frequency (fT), and low output conductance (gd) of the device at low gate work function difference (∆ϕS-D = 0.61 eV) make it a viable candidate for the future low power analog applications.

A Low-Power Low-Skew Current-Mode Clock Distribution Network in 90nm CMOS Technology

2011 ◽  
Author(s):  
Naveen Kumar Kancharapu ◽  
Marshnil Dave ◽  
Veerraju Masimukkula ◽  
Maryam Shojaei Baghini ◽  
Dinesh Kumar Sharma
Keyword(s):  
Low Power ◽  
Distribution Network ◽  
Current Mode ◽  
Cmos Technology ◽  
Clock Distribution ◽  
Clock Distribution Network

What's cool for the future of ultra low power designs?

2010 ◽  
Author(s):  
Nagaraj NS ◽  
John Byler ◽  
Koorosh Nazifi ◽  
Venugopal Puvvada ◽  
Toshiyuki Saito ◽  
...  
Keyword(s):  
Low Power ◽  
Ultra Low Power ◽  
The Future

Simulation Model for Assessing Operational Performance of Current Transformers

2007 ◽  
Vol 18-19 ◽  
pp. 71-77
Author(s):  
I. Sule
Keyword(s):  
Simulation Model ◽  
Current Transformer ◽  
Operational Performance ◽  
Current Transformers ◽  
Correct Operation ◽  
Operational Conditions ◽  
Secondary Current ◽  
Protection Scheme ◽  
The Core ◽  
Instrument Transformers

In determining the correct operation of relays of a protection scheme, proper representation of instrument transformers and their behavior in conditions where there can be saturation, is very critical. The main objective of this paper is to develop simulation model for assessing the operational performance of Current Transformer (CT). In order to test the validity of the developed model, three cases of CT operational conditions were considered, with data collected from Gombe, 330/132/33kV PHCN substation. The simulation results revealed various configuration performance responses that could affect relay protective schemes to different degrees. The CT responses revealed that the secondary current and voltage were distorted when the core flux linkages exceeded the set 9.2 pu saturation limit. It is concluded that the model developed for the CT of interest yield satisfactory results.

CMOS DEVICES ARCHITECTURES AND TECHNOLOGY INNOVATIONS FOR THE NANOELECTRONICS ERA

2006 ◽  
Vol 16 (01) ◽  
pp. 193-219 ◽  
Author(s):  
S. DELEONIBUS ◽  
B. de SALVO ◽  
T. ERNST ◽  
O. FAYNOT ◽  
T. POIROUX ◽  
...  
Keyword(s):  
Low Power ◽  
High Performance ◽  
Gate Dielectric ◽  
Low Voltage ◽  
Short Channel Effects ◽  
Short Channel ◽  
Trade Offs ◽  
Future System ◽  
The Future ◽  
Channel Effects

Innovations in electronics history have been possible because of the strong association of devices and materials research. The demand for low voltage, low power and high performance are the great challenges for engineering of sub 50nm gate length CMOS devices. Functional CMOS devices in the range of 5 nm channel length have been demonstrated. The alternative architectures allowing to increase devices drivability and reduce power are reviewed through the issues to address in gate/channel and substrate, gate dielectric as well as source and drain engineering. HiK gate dielectric and metal gate are among the most strategic options to consider for power consumption and low supply voltage management. It will be very difficult to compete with CMOS logic because of the low series resistance required to obtain high performance. By introducing new materials ( Ge , diamond/graphite Carbon, HiK, …), Si based CMOS will be scaled beyond the ITRS as the future System-on-Chip Platform integrating new disruptive devices. The association of C-diamond with HiK as a combination for new functionalized Buried Insulators, for example, will bring new ways of improving short channel effects and suppress self-heating. That will allow new optimization of Ion-Ioff trade offs. The control of low power dissipation and short channel effects together with high performance will be the major challenges in the future.

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