scholarly journals Physical Unclonable Function (PUF)-Based e-Cash Transaction Protocol (PUF-Cash)

Cryptography ◽  
2019 ◽  
Vol 3 (3) ◽  
pp. 18 ◽  
Author(s):  
Jeff Calhoun ◽  
Cyrus Minwalla ◽  
Charles Helmich ◽  
Fareena Saqib ◽  
Wenjie Che ◽  
...  
Keyword(s):  
Integrated Circuits ◽  
Large Scale ◽  
Model Building ◽  
Security Analysis ◽  
Electronic Money ◽  
Physical Unclonable Functions ◽  
Response Pair ◽  
Field Programmable ◽  
Cash Transaction ◽  
Programmable Gate Arrays

Electronic money (e-money or e-Cash) is the digital representation of physical banknotes augmented by added use cases of online and remote payments. This paper presents a novel, anonymous e-money transaction protocol, built based on physical unclonable functions (PUFs), titled PUF-Cash. PUF-Cash preserves user anonymity while enabling both offline and online transaction capability. The PUF’s privacy-preserving property is leveraged to create blinded tokens for transaction anonymity while its hardware-based challenge–response pair authentication scheme provides a secure solution that is impervious to typical protocol attacks. The scheme is inspired from Chaum’s Digicash work in the 1980s and subsequent improvements. Unlike Chaum’s scheme, which relies on Rivest, Shamir and Adlemans’s (RSA’s) multiplicative homomorphic property to provide anonymity, the anonymity scheme proposed in this paper leverages the random and unique statistical properties of synthesized integrated circuits. PUF-Cash is implemented and demonstrated using a set of Xilinx Zynq Field Programmable Gate Arrays (FPGAs). Experimental results suggest that the hardware footprint of the solution is small, and the transaction rate is suitable for large-scale applications. An in-depth security analysis suggests that the solution possesses excellent statistical qualities in the generated authentication and encryption keys, and it is robust against a variety of attack vectors including model-building, impersonation, and side-channel variants.

scholarly journals FPGAs in Client Compute Hardware

2021 ◽  
Author(s):  
Michael Mattioli
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Application Specific Integrated Circuits ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Performance ◽  
Application Specific

<div>Field-programmable gate arrays (FPGAs) are remarkably versatile. FPGAs are used in a wide variety of applications and industries where use of application-specific integrated circuits (ASICs) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.</div>

Dynamically Reconfigurable Embedded Architectures for Safe Transportation Systems

2014 ◽  
pp. 347-371 ◽  
Author(s):  
Naim Harb ◽  
Smail Niar ◽  
Mazen A. R. Saghir
Keyword(s):  
Integrated Circuits ◽  
Embedded System ◽  
Transportation Systems ◽  
Base System ◽  
Dynamic Partial Reconfiguration ◽  
Dynamically Reconfigurable ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Mtt Algorithm

Embedded system designers are increasingly relying on Field Programmable Gate Arrays (FPGAs) as target design platforms. Today's FPGAs provide high levels of logic density and rich sets of embedded hardware components. They are also inherently flexible and can be easily and quickly modified to meet changing applications or system requirements. On the other hand, FPGAs are generally slower and consume more power than Application-Specific Integrated Circuits (ASICs). However, advances in FPGA architectures, such as Dynamic Partial Reconfiguration (DPR), are helping bridge this gap. DPR enables a portion of an FPGA device to be reconfigured while the device is still operating. This chapter explores the advantage of using the DPR feature in an automotive system. The authors implement a Driver Assistant System (DAS) based on a Multiple Target Tracking (MTT) algorithm as the automotive base system. They show how the DAS architecture can be adjusted dynamically to different scenario situations to provide interesting functionalities to the driver.

Low-Complexity Nonlinear Self-Inverse Permutation for Creating Physically Clone-Resistant Identities

Cryptography ◽  
2020 ◽  
Vol 4 (1) ◽  
pp. 6 ◽  
Author(s):  
Saleh Mulhem ◽  
Ayoub Mars ◽  
Wael Adi
Keyword(s):  
Field Programmable Gate Arrays ◽  
Low Complexity ◽  
System On Chip ◽  
Large Classes ◽  
Physical Unclonable Functions ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
Security Levels ◽  
On Chip

New large classes of permutations over ℤ 2 n based on T-Functions as Self-Inverting Permutation Functions (SIPFs) are presented. The presented classes exhibit negligible or low complexity when implemented in emerging FPGA technologies. The target use of such functions is in creating the so called Secret Unknown Ciphers (SUC) to serve as resilient Clone-Resistant structures in smart non-volatile Field Programmable Gate Arrays (FPGA) devices. SUCs concepts were proposed a decade ago as digital consistent alternatives to the conventional analog inconsistent Physical Unclonable Functions PUFs. The proposed permutation classes are designed and optimized particularly to use non-consumed Mathblock cores in programmable System-on-Chip (SoC) FPGA devices. Hardware and software complexities for realizing such structures are optimized and evaluated for a sample expected target FPGA technology. The attained security levels of the resulting SUCs are evaluated and shown to be scalable and usable even for post-quantum crypto systems.

Safety and Security Analysis for Movable Railroad Bridges

2019 ◽  
Author(s):  
Yongxin Wang ◽  
Matthew Jablonski ◽  
Chaitanya Yavvari ◽  
Zezhou Wang ◽  
Xiang Liu ◽  
...  
Keyword(s):  
Weight Bearing ◽  
Security Analysis ◽  
Primary Objective ◽  
Hydraulic Systems ◽  
Signaling Systems ◽  
Railroad Bridges ◽  
Gate Arrays ◽  
Custom Made ◽  
Field Programmable ◽  
Programmable Gate Arrays

Movable railroad bridges, consisting of lift, bascule, or swing bridges have been used by American rail tracks that cross usable waterways for over a century. Although custom made, movable bridges share many common components and designs. Most of them use weight bearing towers for the movable span using electric or electro-hydraulic systems lift and/or rotate these movable spans. Automated locks hold the bridge in place as soon as the movement stops. The bridge operation, train and ship signaling systems work in synchrony for trains and waterway traffic to be granted safe passage with minimal delay. This synchrony is maintained by using custom-made control systems using Programmable Logic Controllers (PLCs) or Field Programmable Gate Arrays (FPGAs). Controllers located on the movable and the static parts of the bridge communicate using radio and/or wired underwater links sometimes involving marine cables. The primary objective of this paper is to develop a framework to analyze the safety and security of the bridge operating systems and their synchronous operations with railway and waterway systems. We do so by modeling the movable physical components and their control system with the interconnected network system and determine the faults and attacks that may affect their operations. Given the prevalence of attacks against PLCs, FPGAs and controllers, we show a generic way to determine the effect of what if scenarios that may arise due to attacks combined with failures using a case study of a swing bridge.

scholarly journals New Mathblocks-Based Feistel-Like Ciphers for Creating Clone-Resistant FPGA Devices

Cryptography ◽  
2019 ◽  
Vol 3 (4) ◽  
pp. 28 ◽  
Author(s):  
Saleh Mulhem ◽  
Wael Adi
Keyword(s):  
Hard Core ◽  
Major Elements ◽  
Physical Unclonable Functions ◽  
Mapping Functions ◽  
The Public ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Near Future

The Secret Unknown Cipher (SUC) concept was introduced a decade ago as a promising technique for creating pure digital clone-resistant electronic units as alternatives to the traditional non-consistent Physical Unclonable Functions (PUFs). In this work, a very special unconventional cipher design is presented. The design uses hard-core FPGA (Field Programmable Gate Arrays) -Mathblocks available in modern system-on-chip (SoC) FPGAs. Such Mathblocks are often not completely used in many FPGA applications; therefore, it seems wise to make use of such dead (unused) modules to fabricate usable physical security functions for free. Standard cipher designs usually avoid deploying multipliers in the cipher mapping functions due to their high complexity. The main target of this work is to design large cipher classes (e.g., cipher class size >2600) by mainly deploying the FPGA specific mathematical cores. The proposed cipher designs are novel hardware-oriented and new in the public literature, using fully new unusual mapping functions. If a random unknown selection of one cipher out of 2600 ciphers is self-configured in a device, then a Secret Unknown Cipher module is created within a device, making it physically hard to clone. We consider the cipher module for free (for zero cost) if the major elements in the cipher module are making use of unused reanimated Mathblocks. Such ciphers are usable in many future mass products for protecting vehicular units against cloning and modeling attacks. The required self-reconfigurable devices for that concept are not available now; however, they are expected to emerge in the near future.

Field-Programmable Gate Array

2021 ◽  
pp. 257-270
Author(s):  
Mário Pereira Véstias
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Array ◽  
Field Programmable Gate Arrays ◽  
Software Systems ◽  
Reconfigurable Logic ◽  
Memory Cache ◽  
Gate Arrays ◽  
Field Programmable ◽  
Programmable Device ◽  
Programmable Gate Arrays

Field-programmable gate arrays (FPGAs) are integrated circuits whose logic and their interconnections are configurable. These devices are field-programmable, that is, they can be configured by the hardware designer without any intervention of the manufacturer. Most FPGAs can be reprogrammed as many times as we want with a vast variety of digital circuits. Some recent FPGA families are system-on-chips (SoC) with one or more microprocessor cores, memory, cache, and reconfigurable logic allowing the implementation of complex hardware/software systems in a single programmable device. This article focuses on the architecture of FPGAs, including the so called SoC FPGA. It explains the main blocks of the FPGA, how they have evolved along the last decades and the perspectives of next generation FPGAs. It also describes some applicability areas and how its architecture have evolved to adapt to some of these target markets.

scholarly journals FPGAs in Client Compute Hardware

2021 ◽  
Author(s):  
Michael Mattioli
Keyword(s):  
Integrated Circuits ◽  
Field Programmable Gate Arrays ◽  
Gate Arrays ◽  
Application Specific Integrated Circuits ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
And Performance ◽  
Application Specific

<div>Field-programmable gate arrays (FPGAs) are remarkably versatile. FPGAs are used in a wide variety of applications and industries where use of application-specific integrated circuits (ASICs) is less economically feasible. Despite the area, cost, and power challenges designers face when integrating FPGAs into devices, they provide significant security and performance benefits. Many of these benefits can be realized in client compute hardware such as laptops, tablets, and smartphones.</div>

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