scholarly journals Electrical Coupling of Monolithic 3D Inverters (M3INVs): MOSFET and Junctionless FET

2020 ◽  
Vol 11 (1) ◽  
pp. 277
Author(s):  
Tae Jun Ahn ◽  
Yun Seop Yu
Keyword(s):  
Threshold Voltage ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Coupling ◽  
Channel Length ◽  
Oxide Semiconductor ◽  
3 Dimensional ◽  
Noise Margin ◽  
Type Transistor

In this paper, we investigated the electrical coupling between the top and bottom transistors in a monolithic 3-dimensional (3D) inverter (M3INV) stacked vertically with junctionless field-effect transistor (JLFET), which is one of candidates to replace metal-oxide-semiconductor field-effect transistors (MOSFET). Currents, transconductances, and gate capacitances of the top N-type transistor at the different gate voltages of the bottom P-type transistor as a function of thickness of inter-layer dielectric (TILD) and gate channel length (Lg) are simulated using technology computer-aided-design (TCAD). In M3INV stacked vertically with MOSFET (M3INV-MOS) and JLFET (M3INV-JL), the variations of threshold voltage, transconductance, and capacitance increase as TILD decreases and they increase as Lg increases, and thus there is a strong coupling in M3INV at the range of TILD ≤ 30 nm. In M3INV, the coupling between stacked JLFETs in M3INV-JL is larger than that between MOSFETs in M3INV-MOS at the same TILD and Lg. The switching threshold voltage (Vm) and noise margins (NMs) of M3INV are calculated from the voltage transfer characteristics (VTC) simulated with TCAD mixed-mode. As the gate lengths of M3INV-MOS and M3INV-JL increase, the Vm variations increase and decrease, respectively. The smaller the gate lengths of M3INV-NOS and M3INV-JL, the larger and smaller the variation of Vm, respectively. The noise margin of M3INV-MOS is larger and better for inverter characteristics than one of M3INV-JL. M3INV-MOS has less electrical coupling than M3INV-JL.

scholarly journals Investigation of Monolithic 3D Integrated Circuit Inverter with Feedback Field Effect Transistors Using TCAD Simulation

Micromachines ◽  
2020 ◽  
Vol 11 (9) ◽  
pp. 852
Author(s):  
Jong Hyeok Oh ◽  
Yun Seop Yu
Keyword(s):  
Integrated Circuit ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Coupling ◽  
Propagation Delay ◽  
Channel Length ◽  
Memory Window ◽  
Switching Voltage ◽  
Logic Device

The optimal structure and process for the feedback field-effect transistor (FBFET) to operate as a logic device are investigated by using a technology computer-aided design mixed-mode simulator. To minimize the memory window of the FBFET, the channel length (Lch), thickness of silicon body (Tsi), and doping concentration (Nch) of the channel region below the gate are adjusted. As a result, the memory window increases as Lch and Tsi increase, and the memory window is minimum when Nch is approximately 9 × 1019 cm−3. The electrical coupling between the top and bottom tiers of a monolithic 3-dimensional inverter (M3DINV) consisting of an n-type FBFET located at the top tier and a p-type FBFET located at the bottom tier is also investigated. In the M3DINV, we investigate variation of switching voltage with respect to voltage transfer characteristics (VTC), with different thickness values of interlayer dielectrics (TILD), Tsi, Lch, and Nch. The variation of propagation delay of the M3DINV with different TILD, Tsi, Lch, and Nch is also investigated. As a result, the electrical coupling between the stacked FBFETs by TILD can be neglected. The switching voltage gaps increase as Lch and Tsi increase and decrease, respectively. Furthermore, the slopes of VTC of M3DINV increase as Tsi and Nch increase. For transient response, tpHL decrease as Lch, Tsi, and Nch increase, but tpLH increase as Lch and Tsi increase and it is almost the same for Nch.

Electrical Coupling for Monolithic 3-D Integrated Circuit Consisting of Feedback Field-Effect Transistors

2021 ◽  
Vol 21 (8) ◽  
pp. 4293-4297
Author(s):  
Jong Hyeok Oh ◽  
Yun Seop Yu
Keyword(s):  
Threshold Voltage ◽  
Integrated Circuit ◽  
Computer Aided Design ◽  
Field Effect ◽  
Field Effect Transistors ◽  
Electrical Coupling ◽  
Memory Window ◽  
Electrical Characteristics ◽  
Logic Device ◽  
Interlayer Dielectric

In this study, for two cases of monolithic 3-dimensional integrated circuit (M3DIC) consisting of vertically stacked feedback field-effect transistors (FBFETs), the variation of electrical characteristics of the FBFET was presented in terms of electrical coupling by using technology computer aided design (TCAD) simulation. In the Case 1, the M3DIC was composed with an N-type FBFET in an upper tier (tier2) and a P-type FBFET in a lower tier (tier1), and in the Case 2, it was composed with the FBFETs of opposite type of the Case 1 on each tier. To utilize the FBFET as a logic device, the study on optimal structure of FBFET was first performed in terms of reducing a memory window. Based on the N-type FBFET, the memory window was investigated with different values of doping concentration and length of channel region divided into two regions. The threshold voltage, capacitance, and transconductance of two cases of M3DIC composed with proposed FBFET were investigated for different thickness of an interlayer dielectric (TILD). In the Case 1, only for reverse sweep, the threshold voltage of FBFET in the tier2 was changed significantly at TILD < 15 nm, and the capacitance and transconductance of FBFET in the tier2 changed significantly at TILD < 20 nm, as bottom gate voltage applied with 0 and 1 V. In the Case 2, the electrical characteristics of FBFET in the tier2 changed greater than Case 1 with different TILD.

scholarly journals The gamma-ray irradiation sensitivity and dosimetric information instability of RADFET dosimeter

2013 ◽  
Vol 28 (4) ◽  
pp. 415-421 ◽  
Author(s):  
Milic Pejovic
Keyword(s):  
Threshold Voltage ◽  
Field Effect ◽  
Room Temperature ◽  
Gamma Ray ◽  
Field Effect Transistors ◽  
Metal Oxide Semiconductor ◽  
Oxide Semiconductor ◽  
Threshold Voltage Shift ◽  
Voltage Shift ◽  
Gamma Ray Irradiation

The gamma-ray irradiation sensitivity to radiation dose range from 0.5 Gy to 5 Gy and post-irradiation annealing at room and elevated temperatures have been studied for p-channel metal-oxide-semiconductor field effect transistors (also known as radiation sensitive field effect transistors or pMOS dosimeters) with gate oxide thicknesses of 400 nm and 1 mm. The gate biases during the irradiation were 0 and 5 V and 5 V during the annealing. The radiation and the post-irradiation sensitivity were followed by measuring the threshold voltage shift, which was determined by using transfer characteristics in saturation and reader circuit characteristics. The dependence of threshold voltage shift DVT on absorbed radiation dose D and annealing time was assessed. The results show that there is a linear dependence between DVT and D during irradiation, so that the sensitivity can be defined as DVT/D for the investigated dose interval. The annealing of irradiated metal-oxide-semiconductor field effect transistors at different temperatures ranging from room temperature up to 150?C was performed to monitor the dosimetric information loss. The results indicated that the dosimeters information is saved up to 600 hours at room temperature, whereas the annealing at 150?C leads to the complete loss of dosimetric information in the same period of time. The mechanisms responsible for the threshold voltage shift during the irradiation and the later annealing have been discussed also.

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