scholarly journals Scalable Implementation of Hippocampal Network on Digital Neuromorphic System towards Brain-Inspired Intelligence

2020 ◽  
Vol 10 (8) ◽  
pp. 2857
Author(s):  
Wei Sun ◽  
Jiang Wang ◽  
Nan Zhang ◽  
Shuangming Yang
Keyword(s):  
Neural Network ◽  
Large Scale ◽  
Critical Role ◽  
Future Research ◽  
Calculation Algorithm ◽  
Field Programmable ◽  
Innovative System ◽  
Hippocampal Network ◽  
Single Field ◽  
On Chip

In this paper, an expanded digital hippocampal spurt neural network (HSNN) is innovatively proposed to simulate the mammalian cognitive system and to perform the neuroregulatory dynamics that play a critical role in the cognitive processes of the brain, such as memory and learning. The real-time computation of a large-scale peak neural network can be realized by the scalable on-chip network and parallel topology. By exploring the latest research in the field of neurons and comparing with the results of this paper, it can be found that the implementation of the hippocampal neuron model using the coordinate rotation numerical calculation algorithm can significantly reduce the cost of hardware resources. In addition, the rational use of on-chip network technology can further improve the performance of the system, and even significantly improve the network scalability on a single field programmable gate array chip. The neuromodulation dynamics are considered in the proposed system, which can replicate more relevant biological dynamics. Based on the analysis of biological theory and the theory of hardware integration, it is shown that the innovative system proposed in this paper can reproduce the biological characteristics of the hippocampal network and may be applied to brain-inspired intelligent subjects. The study in this paper will have an unexpected effect on the future research of digital neuromorphic design of spike neural network and the dynamics of the hippocampal network.

scholarly journals An Efficient Interconnection System for Neural NOC Using Fault Tolerant Routing Method

2021 ◽  
Vol 2089 (1) ◽  
pp. 012069
Author(s):  
A. Pradeep kumar ◽  
Y. Devendar Reddy ◽  
T. Srinivas Reddy ◽  
K. Jamal
Keyword(s):  
Neural Network ◽  
Large Scale ◽  
Fault Tolerant ◽  
Interconnection Network ◽  
Heavy Traffic ◽  
Data Traffic ◽  
Field Programmable ◽  
Programmable Gate Arrays ◽  
On Chip ◽  
Hardware Costs

Abstract Large scale Neural Network (NN) accelerators typically have multiple processing nodes that can be implemented as a multi-core chip, and can be organized on a network of chips (noise) corresponding to neurons with heavy traffic. Portions of several NoC-based NN chip-to-chip interconnect networks are linked to further enhance overall nerve amplification capacity. Large volumes of multicast on-chip or cross-chip can further complicate the construction of a cross-link network and create a NN barrier of device capacity and resources. In this paper, this refer to inter-chip and inter-chip communication strategies known as neuron connection for NN accelerators. Interconnect for powerful fault-tolerant routing system neural NoC is implemented in this paper. This recommends crossbar arbitration placement, virtual interrupts, and path-based parallelization strategies in terms of intra-chip communications for the virtual channel routing resulting in higher NoC output at lower hardware costs. A lightweight NoC compatible chip-to-chip interconnection scheme is proposed regarding to inter-chip communication for multicast-based data traffic to enable efficient interconnection for NoC-based NN chips. Moreover, the proposed methods will be tested with four Field Programmable Gate Arrays (FPGAs) on four hard-wired deep neural network (DNN) chips. From the experimental results it can be illustrate that a high throguput can obtained effectively by the proposed interconnection network in handling thedata traffic and low DNN through advanced links.

scholarly journals Neural Networks for Infectious Diseases Detection: Prospects and Challenges

2021 ◽  
Author(s):  
Shumaila Javaid ◽  
Nasir Saeed
Keyword(s):  
Neural Network ◽  
Data Privacy ◽  
Critical Role ◽  
Disease Diagnosis ◽  
Future Research ◽  
Detection Accuracy ◽  
Privacy And Security ◽  
Research Directions ◽  
Medical Diagnostic ◽  
Artificial Neural Network Ann

Artificial neural network (ANN) ability to learn, correct errors, and transform a large amount of raw data into useful medical decisions for treatment and care have increased its popularity for enhanced patient safety and quality of care. Therefore, this paper reviews the critical role of ANNs in providing valuable insights for patients’ healthcare decisions and efficient disease diagnosis. We thoroughly review different types of ANNs presented in the existing literature that advanced ANNs adaptation for complex applications. Moreover, we also investigate ANN’s advances for various disease diagnoses and treatments such as viral, skin, cancer, and COVID-19. Furthermore, we propose a novel deep Convolutional Neural Network (CNN) model called ConXNet for improving the detection accuracy of COVID-19 disease. ConXNet is trained and tested using different datasets, and it achieves more than 97% detection accuracy and precision, which is significantly better than existing models. Finally, we highlight future research directions and challenges such as complexity of the algorithms, insufficient available data, privacy and security, and integration of biosensing with ANNs. These research directions require considerable attention for improving the scope of ANNs for medical diagnostic and treatment applications. <br>

Self-Adaptive SoCs for Dependability

2014 ◽  
pp. 1-21
Author(s):  
Liang Guang ◽  
Juha Plosila ◽  
Hannu Tenhunen
Keyword(s):  
Large Scale ◽  
Future Research ◽  
Great Promise ◽  
Primary Concern ◽  
Technology Scaling ◽  
Computing Paradigm ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Self Adaptive

Dependability is a primary concern for emerging billion-transistor SoCs (Systems-on-Chip), especially when the constant technology scaling introduces an increasing rate of faults and errors. Considering the time-dependent device degradation (e.g. caused by aging and run-time voltage and temperature variations), self-adaptive circuits and architectures to improve dependability is promising and very likely inevitable. This chapter extensively surveys existing works on monitoring, decision-making, and reconfiguration addressing different dependability threats to Very Large Scale Integration (VLSI) chips. Centralized, distributed, and hierarchical fault management, utilizing various redundancy schemes and exploiting logical or physical reconfiguration methods, are all examined. As future research directions, the challenge of integrating different error management schemes to account for multifold threats and the great promise of error resilient computing are identified. This chapter provides, for chip designers, much needed insights on applying a self-adaptive computing paradigm to approach dependability on error-prone, cost-sensitive SoCs.

scholarly journals Disaster management and humanitarian logistics – A South African perspective

2011 ◽  
Vol 5 (1) ◽  
Author(s):  
Wilna L. Bean ◽  
Nadia M. Viljoen ◽  
Hans W. Ittmann ◽  
Elza Kekana
Keyword(s):  
South Africa ◽  
South African ◽  
Large Scale ◽  
Critical Role ◽  
Humanitarian Logistics ◽  
Future Research ◽  
The South ◽  
Management Context ◽  
African Perspective ◽  
The Impact

Disasters are becoming an unavoidable part of everyday life throughout the world, including South Africa. Even though South Africa is not a country affected by large-scale disasters such as earthquakes, the impact of disasters in South Africa is aggravated significantly by the vulnerability of people living in informal settlements. Humanitarian logistics, as a ‘new’ sub-field in the supply chain management context, has developed significantly recently to assist in disaster situations. This paper provides an overview of the South African humanitarian logistics context. Even though humanitarian logistics plays a critical role in the aftermath of disasters, it extends far beyond events that can typically be classified as ‘disasters’. Therefore the implication of the South African humanitarian logistics context on future research and collaboration opportunities in South African humanitarian logistics is also discussed. Finally, two recent case studies in the South African humanitarian logistics environment are discussed.

scholarly journals Automatic sleep stage classification with deep residual networks in a mixed-cohort setting

SLEEP ◽  
2020 ◽  
Author(s):  
Alexander Neergaard Olesen ◽  
Poul Jørgen Jennum ◽  
Emmanuel Mignot ◽  
Helge Bjarup Dissing Sorensen
Keyword(s):  
Neural Network ◽  
Large Scale ◽  
Deep Neural Network ◽  
Sleep Stage ◽  
Scoring Systems ◽  
Training Data ◽  
Future Research ◽  
Small Scale ◽  
Sleep Stage Scoring ◽  
Single Cohort

Abstract Study Objectives Sleep stage scoring is performed manually by sleep experts and is prone to subjective interpretation of scoring rules with low intra- and interscorer reliability. Many automatic systems rely on few small-scale databases for developing models, and generalizability to new datasets is thus unknown. We investigated a novel deep neural network to assess the generalizability of several large-scale cohorts. Methods A deep neural network model was developed using 15,684 polysomnography studies from five different cohorts. We applied four different scenarios: (1) impact of varying timescales in the model; (2) performance of a single cohort on other cohorts of smaller, greater, or equal size relative to the performance of other cohorts on a single cohort; (3) varying the fraction of mixed-cohort training data compared with using single-origin data; and (4) comparing models trained on combinations of data from 2, 3, and 4 cohorts. Results Overall classification accuracy improved with increasing fractions of training data (0.25%: 0.782 ± 0.097, 95% CI [0.777–0.787]; 100%: 0.869 ± 0.064, 95% CI [0.864–0.872]), and with increasing number of data sources (2: 0.788 ± 0.102, 95% CI [0.787–0.790]; 3: 0.808 ± 0.092, 95% CI [0.807–0.810]; 4: 0.821 ± 0.085, 95% CI [0.819–0.823]). Different cohorts show varying levels of generalization to other cohorts. Conclusions Automatic sleep stage scoring systems based on deep learning algorithms should consider as much data as possible from as many sources available to ensure proper generalization. Public datasets for benchmarking should be made available for future research.

scholarly journals Toward Robust Cognitive 3D Brain-Inspired Cross-Paradigm System

2021 ◽  
Vol 15 ◽  
Author(s):  
Abderazek Ben Abdallah ◽  
Khanh N. Dang
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Large Scale ◽  
Three Dimensional ◽  
Network On Chip ◽  
Spike Timing ◽  
Dimensional Structure ◽  
Spiking Neural Network ◽  
3D Ics ◽  
On Chip

Spiking Neuromorphic systems have been introduced as promising platforms for energy-efficient spiking neural network (SNNs) execution. SNNs incorporate neuronal and synaptic states in addition to the variant time scale into their computational model. Since each neuron in these networks is connected to many others, high bandwidth is required. Moreover, since the spike times are used to encode information in SNN, a precise communication latency is also needed, although SNN is tolerant to the spike delay variation in some limits when it is seen as a whole. The two-dimensional packet-switched network-on-chip was proposed as a solution to provide a scalable interconnect fabric in large-scale spike-based neural networks. The 3D-ICs have also attracted a lot of attention as a potential solution to resolve the interconnect bottleneck. Combining these two emerging technologies provides a new horizon for IC design to satisfy the high requirements of low power and small footprint in emerging AI applications. Moreover, although fault-tolerance is a natural feature of biological systems, integrating many computation and memory units into neuromorphic chips confronts the reliability issue, where a defective part can affect the overall system's performance. This paper presents the design and simulation of R-NASH-a reliable three-dimensional digital neuromorphic system geared explicitly toward the 3D-ICs biological brain's three-dimensional structure, where information in the network is represented by sparse patterns of spike timing and learning is based on the local spike-timing-dependent-plasticity rule. Our platform enables high integration density and small spike delay of spiking networks and features a scalable design. R-NASH is a design based on the Through-Silicon-Via technology, facilitating spiking neural network implementation on clustered neurons based on Network-on-Chip. We provide a memory interface with the host CPU, allowing for online training and inference of spiking neural networks. Moreover, R-NASH supports fault recovery with graceful performance degradation.

scholarly journals Rethinking arithmetic for deep neural networks

2020 ◽  
Vol 378 (2166) ◽  
pp. 20190051
Author(s):  
G. A. Constantinides
Keyword(s):  
Neural Network ◽  
Neural Networks ◽  
Directed Graph ◽  
High Performance ◽  
Deep Neural Networks ◽  
Numerical Algorithms ◽  
Future Research ◽  
Data Coding ◽  
Open Questions ◽  
Field Programmable

We consider efficiency in the implementation of deep neural networks. Hardware accelerators are gaining interest as machine learning becomes one of the drivers of high-performance computing. In these accelerators, the directed graph describing a neural network can be implemented as a directed graph describing a Boolean circuit. We make this observation precise, leading naturally to an understanding of practical neural networks as discrete functions, and show that the so-called binarized neural networks are functionally complete. In general, our results suggest that it is valuable to consider Boolean circuits as neural networks , leading to the question of which circuit topologies are promising. We argue that continuity is central to generalization in learning, explore the interaction between data coding, network topology, and node functionality for continuity and pose some open questions for future research. As a first step to bridging the gap between continuous and Boolean views of neural network accelerators, we present some recent results from our work on LUTNet, a novel Field-Programmable Gate Array inference approach. Finally, we conclude with additional possible fruitful avenues for research bridging the continuous and discrete views of neural networks. This article is part of a discussion meeting issue ‘Numerical algorithms for high-performance computational science’.

scholarly journals Revisiting the High-Performance Reconfigurable Computing for Future Datacenters

2020 ◽  
Vol 12 (4) ◽  
pp. 64 ◽  
Author(s):  
Qaiser Ijaz ◽  
El-Bay Bourennane ◽  
Ali Kashif Bashir ◽  
Hira Asghar
Keyword(s):  
Reconfigurable Computing ◽  
High Performance ◽  
Large Scale ◽  
Open Problems ◽  
Communication Architecture ◽  
Field Programmable ◽  
Large Scale Integration ◽  
On Chip ◽  
Scale Integration ◽  
Standard Terms

Modern datacenters are reinforcing the computational power and energy efficiency by assimilating field programmable gate arrays (FPGAs). The sustainability of this large-scale integration depends on enabling multi-tenant FPGAs. This requisite amplifies the importance of communication architecture and virtualization method with the required features in order to meet the high-end objective. Consequently, in the last decade, academia and industry proposed several virtualization techniques and hardware architectures for addressing resource management, scheduling, adoptability, segregation, scalability, performance-overhead, availability, programmability, time-to-market, security, and mainly, multitenancy. This paper provides an extensive survey covering three important aspects—discussion on non-standard terms used in existing literature, network-on-chip evaluation choices as a mean to explore the communication architecture, and virtualization methods under latest classification. The purpose is to emphasize the importance of choosing appropriate communication architecture, virtualization technique and standard language to evolve the multi-tenant FPGAs in datacenters. None of the previous surveys encapsulated these aspects in one writing. Open problems are indicated for scientific community as well.

scholarly journals Attention bias toward threat is associated with exaggerated fear expression and impaired extinction in PTSD

2011 ◽  
Vol 42 (3) ◽  
pp. 533-543 ◽  
Author(s):  
N. Fani ◽  
E. B. Tone ◽  
J. Phifer ◽  
S. D. Norrholm ◽  
B. Bradley ◽  
...  
Keyword(s):  
Neural Network ◽  
Critical Role ◽  
Network Models ◽  
Fear Learning ◽  
Future Research ◽  
Post Traumatic Stress ◽  
Neural Network Models ◽  
Post Traumatic ◽  
Fear Potentiated Startle ◽  
The Relationship

BackgroundPost-traumatic stress disorder (PTSD) develops in a minority of traumatized individuals. Attention biases to threat and abnormalities in fear learning and extinction are processes likely to play a critical role in the creation and/or maintenance of PTSD symptomatology. However, the relationship between these processes has not been established, particularly in highly traumatized populations; understanding their interaction can help inform neural network models and treatments for PTSD.MethodAttention biases were measured using a dot probe task modified for use with our population; task stimuli included photographs of angry facial expressions, which are emotionally salient threat signals. A fear-potentiated startle paradigm was employed to measure atypical physiological response during acquisition and extinction phases of fear learning. These measures were administered to a sample of 64 minority (largely African American), highly traumatized individuals with and without PTSD.ResultsParticipants with PTSD demonstrated attention biases toward threat; this attentional style was associated with exaggerated startle response during fear learning and early and middle phases of extinction, even after accounting for the effects of trauma exposure.ConclusionsOur findings indicate that an attentional bias toward threat is associated with abnormalities in ‘fear load’ in PTSD, providing seminal evidence for an interaction between these two processes. Future research combining these behavioral and psychophysiological techniques with neuroimaging will be useful toward addressing how one process may modulate the other and understanding whether these phenomena are manifestations of dysfunction within a shared neural network. Ultimately, this may serve to inform PTSD treatments specifically designed to correct these atypical processes.

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