scholarly journals A Low Quantum Cost Implementation of Reversible Binary-Coded-Decimal Adder

2020 ◽  
Vol 64 (4) ◽  
pp. 343-351
Author(s):  
Sheba Diamond Thabah ◽  
Prabir Saha
Keyword(s):  
Quantum Computer ◽  
Research Area ◽  
Quantum Gates ◽  
Quantum Cost ◽  
Performance Parameters ◽  
Hardware Complexity ◽  
Proper Selection ◽  
Technical Literature ◽  
Gate Count ◽  
Decimal Adder

The prediction and forthcoming of a quantum computer into the real-world is the much gained research area over the last decades, which initiated the usefulness and profit of reversible computation because of its potentiality to reduce power consumption in designing arithmetic circuits. In this paper, two design approaches are proposed for the design of a reversible Binary-Coded-Decimal adder. The first approach is implemented and realized from reversible gates proposed by researchers in the technical literature capable of breaking down into primitive quantum gates, whereas the second approach is realized from the existing synthesizable reversible gates only. Parallel implementations of such circuits have been carried out through the proper selection and arrangements of the gates to improve the reversible performance parameters. The proposed design approaches offer a low quantum cost along-with lower delay and hardware complexity for any n-digit addition. Analysis results of proposed design 1 show appreciable improvements over gate count, quantum cost, and delay by at least 9 %, 17 %, and 26 % respectively, whereas, the proposed design 2 show that the results significantly improve the parameters (gate count, quantum cost, and delay) by at least 45 %, 33 %, and 50 % respectively compared to existing counterparts found in the literature.

scholarly journals Comparative Review on Efficient Design of Reversible Sequential Circuits based on Optimization Parameters

2021 ◽  
Vol 23 (09) ◽  
pp. 1313-1325
Author(s):  
Gobinda Karmakar ◽  
◽  
Dr. Saroj Kumar Biswas ◽  
Dr. Ardhendu Mandal ◽  
Arijit Bhattacharya ◽  
...  
Keyword(s):  
Research Area ◽  
Sequential Circuits ◽  
Quantum Cost ◽  
Efficient Design ◽  
Hardware Complexity ◽  
Constant Input ◽  
Reversible Computing ◽  
Main Challenge ◽  
Comparative Review ◽  
Optimization Parameters

Reversible computing, a well known research area in the field of computer science. One of the aims of reversible computing is to design low power digital circuits that dissipates no energy to heat. The main challenge of designing reversible circuits is to optimize the parameters which make the design costly. In this paper, we review different designs of efficient reversible sequential circuits and prepare a comparative statement based on eight optimization parameters such as Quantum Cost (QC), Delay (del), Garbage Output (GO), Constant Input (CI), Gate Level (GL), Number of Gate (NoG), Type of Gate (ToG), Hardware Complexity (HC) of Circuit.

Efficient reversible quantum design of sig-magnitude to two's complement converters

2020 ◽  
Vol 20 (9&10) ◽  
pp. 747-765
Author(s):  
F. Orts ◽  
G. Ortega ◽  
E.M. E.M. Garzon
Keyword(s):  
Quantum Computing ◽  
Scientific Community ◽  
Quantum Computer ◽  
Fault Tolerant ◽  
State Of The Art ◽  
The Other ◽  
Quantum Computers ◽  
Binary Number ◽  
Quantum Cost ◽  
The One

Despite the great interest that the scientific community has in quantum computing, the scarcity and high cost of resources prevent to advance in this field. Specifically, qubits are very expensive to build, causing the few available quantum computers are tremendously limited in their number of qubits and delaying their progress. This work presents new reversible circuits that optimize the necessary resources for the conversion of a sign binary number into two's complement of N digits. The benefits of our work are two: on the one hand, the proposed two's complement converters are fault tolerant circuits and also are more efficient in terms of resources (essentially, quantum cost, number of qubits, and T-count) than the described in the literature. On the other hand, valuable information about available converters and, what is more, quantum adders, is summarized in tables for interested researchers. The converters have been measured using robust metrics and have been compared with the state-of-the-art circuits. The code to build them in a real quantum computer is given.

OPTIMIZED REVERSIBLE MULTIPLIER CIRCUIT

2009 ◽  
Vol 18 (02) ◽  
pp. 311-323 ◽  
Author(s):  
MAJID HAGHPARAST ◽  
MAJID MOHAMMADI ◽  
KEIVAN NAVI ◽  
MOHAMMAD ESHGHI
Keyword(s):  
Dna Computing ◽  
Full Adder ◽  
Logic Circuits ◽  
Optical Information ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Cmos Design ◽  
Fair Comparison ◽  
Low Power Cmos ◽  
Significant Attention

Reversible logic circuits have received significant attention in quantum computing, low power CMOS design, optical information processing, DNA computing, bioinformatics, and nanotechnology. This paper presents two new 4 × 4 bit reversible multiplier designs which have lower hardware complexity, less garbage bits, less quantum cost and less constant inputs than previous ones, and can be generalized to construct efficient reversible n × n bit multipliers. An implementation of reversible HNG is also presented. This implementation shows that the full adder design using HNG is one of the best designs in term of quantum cost. An implementation of MKG is also presented in order to have a fair comparison between our proposed reversible multiplier designs and the existing counterparts. The proposed reversible multipliers are optimized in terms of quantum cost, number of constant inputs, number of garbage outputs and hardware complexity. They can be used to construct more complex systems in nanotechnology.

scholarly journals Low Quantum Cost Realization of Reversible Binary-Coded-Decimal Adder

2020 ◽  
Vol 167 ◽  
pp. 1437-1443
Author(s):  
Sheba Diamond Thabah ◽  
Prabir Saha
Keyword(s):  
Quantum Cost ◽  
Decimal Adder

Design of quaternary quantum reversible half subtractor, full subtractor and n-qudit borrow ripple subtractor

2019 ◽  
Vol 17 (05) ◽  
pp. 1950048
Author(s):  
Abdollah Norouzi Doshanlou ◽  
Majid Haghparast ◽  
Mehdi Hosseinzadeh ◽  
Midia Reshadi
Keyword(s):  
System Performance ◽  
Quantum Cost ◽  
Hardware Complexity ◽  
Constant Input ◽  
Comparison Results ◽  
Garbage Output ◽  
First Time

In this paper, we proposed novel plans of quaternary quantum reversible half and full subtractor circuits. The subtractor element is the essential part of the ALU in the digital computational devices. Thus, the improvement of subtractor block has a significant impact on the overall system performance. According to the comparison results, the proposed quaternary quantum half and full subtractor circuits show tremendous improvement in quantum cost, hardware complexity, number of constant input and garbage output as compared to their counterparts. Moreover, for the first time, the quaternary quantum borrow ripple subtractor structure is realized using the proposed quaternary quantum half and full subtractor circuits.

scholarly journals An Algorithm of Quantum Restricted Boltzmann Machine Network Based on Quantum Gates and Its Application

2015 ◽  
Vol 2015 ◽  
pp. 1-7
Author(s):  
Peilin Zhang ◽  
Sheng Li ◽  
Yu Zhou
Keyword(s):  
Quantum Computer ◽  
Quantum Circuit ◽  
Classification Performance ◽  
Generative Model ◽  
Restricted Boltzmann Machine ◽  
Quantum Gates ◽  
Boltzmann Machine ◽  
Discriminative Models

We present an algorithm of quantum restricted Boltzmann machine network based on quantum gates. The algorithm is used to initialize the procedure that adjusts the qubit and weights. After adjusting, the network forms an unsupervised generative model that gives better classification performance than other discriminative models. In addition, we show how the algorithm can be constructed with quantum circuit for quantum computer.

D-Wave and predecessors: From simulated to quantum annealing

2014 ◽  
Vol 12 (03) ◽  
pp. 1430002 ◽  
Author(s):  
Eliahu Cohen ◽  
Boaz Tamir
Keyword(s):  
Genetic Algorithm ◽  
Image Processing ◽  
Large Scale ◽  
Quantum Computer ◽  
Research Area ◽  
Hill Climbing ◽  
Quantum Annealing ◽  
Challenging Research ◽  
Computer Based ◽  
D Wave

On May 2011, D-Wave Systems Inc. announced "D-Wave One", as "the world's first commercially available quantum computer". No wonder this adiabatic quantum computer based on 128-qubit chip-set provoked an immediate controversy. Over the last 40 years, quantum computation has been a very promising yet challenging research area, facing major difficulties producing a large scale quantum computer. Today, after Google has purchased "D-Wave Two" containing 512 qubits, criticism has only increased. In this work, we examine the theory underlying the D-Wave, seeking to shed some light on this intriguing quantum computer. Starting from classical algorithms such as Metropolis algorithm, genetic algorithm (GA), hill climbing and simulated annealing, we continue to adiabatic computation and quantum annealing towards better understanding of the D-Wave mechanism. Finally, we outline some applications within the fields of information and image processing. In addition, we suggest a few related theoretical ideas and hypotheses.

scholarly journals On The Implementation of Densely Packed Decimal Number System Based Adder: Prospects and Challenges

2021 ◽  
Vol 25 (1) ◽  
pp. 20-30
Author(s):  
Srikant Kumar Beura ◽  
◽  
Rekib Uddin Ahmed ◽  
Bishnulatpam Pushpa Devi ◽  
Prabir Saha ◽  
...  
Keyword(s):  
Circuit Simulation ◽  
Number System ◽  
Decimal Digit ◽  
Performance Parameters ◽  
Design Technique ◽  
Digit Number ◽  
Time Saving ◽  
Decimal Number ◽  
Decimal Adder ◽  
Pros And Cons

Decimal digit number computation, through bit compression methodology, offers space and time saving, which can be incurred by the Chen-Ho and Densely Packed Decimal (DPD) coding techniques. Such coding techniques have a property of bit compression, like, three decimal digits can be represented by 10 bits instead of 12 bits in binary coded decimal (BCD) format. The compression has been obtained through the elimination of the redundant 0’s from BCD representation. This manuscript reports the pros and cons of the techniques mentioned above. The logic level functionalities have been examined through MATLAB, whereas circuit simulation has been erified through Cadence Spectre. Performance parameters (such as delay, power consumption) have been evaluated through CMOS gpdk45 nm technology. Furthermore, the best design has been chosen from them, and the decimal adder design technique has been incorporated in this paper.

scholarly journals Synthesis of quantum circuits in Linear Nearest neighbor Model using Positive Davio Lattices

2011 ◽  
Vol 24 (1) ◽  
pp. 71-87 ◽  
Author(s):  
Marek Perkowski ◽  
Martin Lukac ◽  
Dipal Shah ◽  
Michitaka Kameyama
Keyword(s):  
Nearest Neighbor ◽  
Dimensional Space ◽  
Synthesis Method ◽  
Logic Synthesis ◽  
Quantum Circuits ◽  
Quantum Gates ◽  
Synthesis Methods ◽  
Cost Models ◽  
Quantum Cost ◽  
One Dimensional

We present a logic synthesis method based on lattices that realize quantum arrays in One-Dimensional Ion Trap technology. This means that all gates are built from 2x2 quantum primitives that are located only on neighbor qubits in a one-dimensional space (called also vector of qubits or Linear Nearest Neighbor (LNN) architecture). The Logic circuits designed by the proposed method are realized only with 3*3 Toffoli, Feynman and NOT quantum gates and the usage of the commonly used multi-input Toffoli gates is avoided. This realization method of quantum circuits is different from most of reversible circuits synthesis methods from the literature that use only high level quantum cost based on the number of quantum gates. Our synthesis approach applies to both standard and LNN quantum cost models. It leads to entirely new CAD algorithms for circuit synthesis and substantially decreases the quantum cost for LNN quantum circuits. The drawback of synthesizing circuits in the presented LNN architecture is the addition of ancilla qubits.

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