Analysis of Inner-consistency of BDS Broadcast Ephemeris Parameters and their Performance Improvement

2017 ◽  
Author(s):  
Junping Chen ◽  
Qian Chen ◽  
Bin Wang ◽  
Sainan Yang ◽  
Yize Zhang ◽  
...  
Keyword(s):  
Performance Improvement ◽  
Broadcast Ephemeris ◽  
Broadcast Ephemeris Parameters

scholarly journals Study on Optimal Broadcast Ephemeris Parameters for GEO/IGSO Navigation Satellites

Sensors ◽  
2020 ◽  
Vol 20 (22) ◽  
pp. 6544
Author(s):  
Jin Haeng Choi ◽  
Gimin Kim ◽  
Deok Won Lim ◽  
Chandeok Park
Keyword(s):  
Optimal Parameter ◽  
Orbital Plane ◽  
Least Square ◽  
Broadcast Ephemeris ◽  
Curve Fit ◽  
Global Positioning ◽  
Geo Satellites ◽  
Broadcast Ephemeris Parameters ◽  
Orbit Types ◽  
Range Error

This paper proposes new sets of suitable broadcast ephemeris parameters for geosynchronous (GEO) and inclined geosynchronous (IGSO) navigation satellites (NSs). Despite the increasing number of GEO and IGSO NSs, global positioning system (GPS)-type ephemeris parameters are still widely used for them. In an effort to provide higher fit accuracy, we analyze a variety of broadcast ephemeris parameters for GEO and IGSO satellites along with their orbital characteristics and propose optimal sets of parameters. Nonsingular elements and orbital plane rotation are adopted for alleviating/avoiding the singularity issues of GEO satellites. On the basis of 16 parameters of GPS LNAV, we add one to four parameters out of 28 correction ones to determine optimal sets of ephemeris parameters providing higher accuracy. All possible parameter sets are tested with the least-square curve fit for four BeiDou GEOs and six BeiDou IGSOs. Their fit accuracies are compared to determine the optimal broadcast ephemeris parameters that provide minimum fit errors. The set of optimal ephemeris parameters depends on the type of orbit. User range error (URE) accuracies of the proposed optimal ephemeris parameters ensure results within 2.4 cm for IGSO and 3.8 cm for GEO NSs. Moreover, the experimental results present common parameter sets for both IGSO and GEO for compatibility and uniformity. Compared with four conventional/well-known sets of ephemeris parameters for BeiDou, our proposed parameters can enhance accuracies of up to 34.5% in terms of URE. We also apply the proposed optimal parameter sets to one GEO and three IGSO satellites of QZSS. The effects of fitting intervals, number of parameters, total bits, and orbit types on the fit accuracy are addressed in detail.

Satellite autonomous navigation algorithm analysis based on broadcast ephemeris parameters

2015 ◽  
Vol 45 (7) ◽  
pp. 079512-079512 ◽  
Author(s):  
XiaoLin JIA ◽  
Yue MAO ◽  
XianBing WU ◽  
XiaoYong SONG ◽  
XiaoGong HU ◽  
...  
Keyword(s):  
Autonomous Navigation ◽  
Algorithm Analysis ◽  
Broadcast Ephemeris ◽  
Navigation Algorithm ◽  
Broadcast Ephemeris Parameters

Peningkatan kinerja guru dalam pembelajaran di kelas melalui supervisi edukatif Kolaboratif secara periodik MIS Lawe kongker Tahun pelajaran 2019/2020

2020 ◽  
Vol 1 (3) ◽  
pp. 316-324
Author(s):  
Syukrani Kadir
Keyword(s):  
Student Learning ◽  
Performance Improvement ◽  
Teacher Performance ◽  
Learning Cycle ◽  
Learning Achievement ◽  
Educational Supervision ◽  
Average Action ◽  
Learning Plans

periodically in preparing learning plans, implementing learning, assessing learning achievement, carrying out follow-up assessments of student learning achievement that can improve teacher performance. This performance improvement is through periodic collaborative educational supervision. Based on the results of educational supervision in cycle I and cycle II, teacher performance increased, namely in cycle I, teacher performance in preparing learning plans in cycle I reached 71.98%, while cycle II was 92.44%. Teacher performance in implementing learning cycle I reached 72.44% while cycle II reached 93.81%. Teacher performance in assessing learning achievement in cycle Im reached 81.30% while cycle II was 90.56%. Teacher performance in carrying out follow-up assessments of student learning achievement in the first cycle reached 59.76% while the second cycle was 83.00%. Thus, the average action cycle II was above 75.00%. Based on the results of this study, it can be concluded that the teacher's performance has increased in preparing learning plans, implementing learning, assessing learning achievement, carrying out follow-up assessments of student learning achievement.

CONVEYOR MODEL AND IMPLEMENTATION OF THE REAL NUMBERS ADDER ON FPGA

2020 ◽  
Vol 33 (109) ◽  
pp. 21-31
Author(s):  
І. Ya. Zeleneva ◽  
Т. V. Golub ◽  
T. S. Diachuk ◽  
А. Ye. Didenko
Keyword(s):  
Performance Improvement ◽  
Experimental Studies ◽  
Production Costs ◽  
Floating Point ◽  
Computing Device ◽  
Quartus Ii ◽  
Functional Blocks ◽  
Mental Testing ◽  
Processor Cores ◽  
Floating Point Numbers

The purpose of these studies is to develop an effective structure and internal functional blocks of a digital computing device – an adder, that performs addition and subtraction operations on floating- point numbers presented in IEEE Std 754TM-2008 format. To improve the characteristics of the adder, the circuit uses conveying, that is, division into levels, each of which performs a specific action on numbers. This allows you to perform addition / subtraction operations on several numbers at the same time, which increas- es the performance of calculations, and also makes the adder suitable for use in modern synchronous cir- cuits. Each block of the conveyor structure of the adder on FPGA is synthesized as a separate project of a digital functional unit, and thus, the overall task is divided into separate subtasks, which facilitates experi- mental testing and phased debugging of the entire device. Experimental studies were performed using EDA Quartus II. The developed circuit was modeled on FPGAs of the Stratix III and Cyclone III family. An ana- logue of the developed circuit was a functionally similar device from Altera. A comparative analysis is made and reasoned conclusions are drawn that the performance improvement is achieved due to the conveyor structure of the adder. Implementation of arithmetic over the floating-point numbers on programmable logic integrated cir- cuits, in particular on FPGA, has such advantages as flexibility of use and low production costs, and also provides the opportunity to solve problems for which there are no ready-made solutions in the form of stand- ard devices presented on the market. The developed adder has a wide scope, since most modern computing devices need to process floating-point numbers. The proposed conveyor model of the adder is quite simple to implement on the FPGA and can be an alternative to using built-in multipliers and processor cores in cases where the complex functionality of these devices is redundant for a specific task.

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