scholarly journals Development of Jump Markovian Dynamic Models of Low Cost Digital Duty-Cycle Modulation Drivers For Target System-on-Chip Devices

2020 ◽  
pp. 364-372
Author(s):  
Jean Mbihi ◽  
Léandre Nneme Nneme
Keyword(s):  
Dynamic Model ◽  
Duty Cycle ◽  
Dynamic Models ◽  
Low Cost ◽  
Digital Simulation ◽  
System On Chip ◽  
Target System ◽  
Digital To Analog Converter ◽  
Usb Communication ◽  
On Chip

In this paper, a novel building algorithmic scheme of DDCM (duty-cycle modulation) drivers is presented. It is modelled in the analog domain as a continuous time jump Markovian dynamic model, with a deterministic two-state Markov chain. An equivalent discrete jump dynamic model is computed using pole-zero matching transform. Then, the resulting digital iterative algorithm, consists of simple digital operators and structures. The proposed DDCM algorithm is simulated under Matlab framework, and implemented using Arduino IDE-C++ with uploading into an ESP32 system-on-chip (SoC) device. The monitoring device connected to the ESP32 via an USB communication cable is an Arduino/IDE virtual monitor. It is configured for 230400 bauds communication. A low cost ESP32-based DAC (digital-to-analog converter), is virtually implemented and well tested as a case study of the proposed new generation of DDCM drivers. Matlab digital simulation results and ESP32 processing and virtual monitoring results are presented and discussed, in order to show the realistic nature and the great challenge the proposed DDCM algorithmic scheme for SOC devices.

First Intel Low-Cost IA Atom-based System-On-Chip for Nettop/Netbook

2009 ◽  
Author(s):  
Suphachai Sutanthavibul ◽  
Suresh Kumar Perabala
Keyword(s):  
Low Cost ◽  
System On Chip ◽  
On Chip

scholarly journals Low Complexity System on Chip Design to Acquire Signals from MOS Gas Sensor Applications

Sensors ◽  
2021 ◽  
Vol 21 (19) ◽  
pp. 6552
Author(s):  
Juan B. Talens ◽  
Jose Pelegri-Sebastia ◽  
Maria Jose Canet
Keyword(s):  
Gas Sensor ◽  
Low Voltage ◽  
Low Cost ◽  
Low Complexity ◽  
System On Chip ◽  
Working Environment ◽  
Sigma Delta ◽  
Sensor Applications ◽  
Analog Signals ◽  
On Chip

Analog signals from gas sensors are used to recognize all types of VOC (Volatile Organic Compound) substances, such as toxic gases, tobacco or ethanol. The processes to recognize these substances include acquisition, treatment and machine learning for classification, which can all be efficiently implemented on a Field Programmable Gate Array (FPGA) aided by Low-Voltage Differential Signaling (LVDS). This article proposes a low-cost 11-bit effective number of bits (ENOB) sigma-delta Analog to Digital Converter (ADC), with an SNR of 75.97 dB and an SFDR of 72.28 dB, whose output is presented on screen in real time, thanks to the use of a Linux System on Chip (SoC) system that enables parallelism, high-level programming and provides a working environment for the scientific treatment of gas sensor signals. The high frequency achieved by the implemented ADC allows for multiplexing the capture of several analog signals with an optimal resolution. Additionally, several ADCs can be implemented in the same FPGA so several analog signals can be digitalized in parallel.

Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽  
2020 ◽  
Vol ahead-of-print (ahead-of-print) ◽  
Author(s):  
Chen Kuilin ◽  
Feng Xi ◽  
Fu Yingchun ◽  
Liu Liang ◽  
Feng Wennan ◽  
...  
Keyword(s):  
Parallel Processing ◽  
High Speed ◽  
High Performance ◽  
Low Cost ◽  
Data Encryption ◽  
System On Chip ◽  
Content Type ◽  
Data Encryption Standard ◽  
Peripheral Component Interconnect ◽  
On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

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