An Analysis of Small-Signal Source-Body Resistance Effect on RF MOSFETs for Low-Cost System-on-Chip (SoC) Applications

Decreasing the bill of materials for an electronic device saves development time, money and space. The integration of more and more functions not only on the chip (SoC; system on chip) but also in the package (SiP; system in package) is therefore a natural and very important step in the devolvement of micro electronics. Realizing the goal of Ambient Intelligence requires low cost system solutions where all necessary components are integrated. The future will be a combination of “System on Chip”- and “System in Package” solution called as “Heterogeneous Integration”. As far as technical and economical feasible “System on Chip” solutions will be chosen, the adoption to various applications and the integration of highly complex systems containing non-electronic functions will be carried out more cost efficiently, with a high degree of miniaturization and flexibility in “Heterogeneous Integration”. “Heterogeneous Integration” integrates several chips or components in one package (system in package or SiP) and carries out the interface to the application environment. This paper will summarize a variety of heterogeneous integration technologies researched at Fraunhofer IZM with a strong focus on embedding in printed circuit boards and embedding in molded reconfigured wafers – looking also on the requirements of sensor packaging. Not only the technological principles but also specific material demands and necessary processes as 3D routing and also 3D interconnection will be discussed in detail. Application examples and technology demonstrators from will be shown to demonstrate technological potential and challenges of miniaturized heterogeneous integration by embedding from a European perspective.

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First Intel Low-Cost IA Atom-based System-On-Chip for Nettop/Netbook

10.1109/asqed.2009.5206293 ◽

2009 ◽

Cited By ~ 2

Author(s):

Suphachai Sutanthavibul ◽

Suresh Kumar Perabala

Keyword(s):

Low Cost ◽

System On Chip ◽

On Chip

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Low Complexity System on Chip Design to Acquire Signals from MOS Gas Sensor Applications

Sensors ◽

10.3390/s21196552 ◽

2021 ◽

Vol 21 (19) ◽

pp. 6552

Author(s):

Juan B. Talens ◽

Jose Pelegri-Sebastia ◽

Maria Jose Canet

Keyword(s):

Gas Sensor ◽

Low Voltage ◽

Low Cost ◽

Low Complexity ◽

System On Chip ◽

Working Environment ◽

Sigma Delta ◽

Sensor Applications ◽

Analog Signals ◽

On Chip

Analog signals from gas sensors are used to recognize all types of VOC (Volatile Organic Compound) substances, such as toxic gases, tobacco or ethanol. The processes to recognize these substances include acquisition, treatment and machine learning for classification, which can all be efficiently implemented on a Field Programmable Gate Array (FPGA) aided by Low-Voltage Differential Signaling (LVDS). This article proposes a low-cost 11-bit effective number of bits (ENOB) sigma-delta Analog to Digital Converter (ADC), with an SNR of 75.97 dB and an SFDR of 72.28 dB, whose output is presented on screen in real time, thanks to the use of a Linux System on Chip (SoC) system that enables parallelism, high-level programming and provides a working environment for the scientific treatment of gas sensor signals. The high frequency achieved by the implemented ADC allows for multiplexing the capture of several analog signals with an optimal resolution. Additionally, several ADCs can be implemented in the same FPGA so several analog signals can be digitalized in parallel.

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Design and implementation of system-on-chip for peripheral component interconnect express encryption card based on multiple algorithms

Circuit World ◽

10.1108/cw-02-2019-0013 ◽

2020 ◽

Vol ahead-of-print (ahead-of-print) ◽

Author(s):

Chen Kuilin ◽

Feng Xi ◽

Fu Yingchun ◽

Liu Liang ◽

Feng Wennan ◽

...

Keyword(s):

Parallel Processing ◽

High Speed ◽

High Performance ◽

Low Cost ◽

Data Encryption ◽

System On Chip ◽

Content Type ◽

Data Encryption Standard ◽

Peripheral Component Interconnect ◽

On Chip

Purpose The data protection is always a vital problem in the network era. High-speed cryptographic chip is an important part to ensure data security in information interaction. This paper aims to provide a new peripheral component interconnect express (PCIe) encryption card solution with high performance, high integration and low cost. Design/methodology/approach This work proposes a System on Chip architecture scheme of high-speed cryptographic chip for PCIe encryption card. It integrated CPU, direct memory access, the national and international cipher algorithm (data encryption standard/3 data encryption standard, Rivest–Shamir–Adleman, HASH, SM1, SM2, SM3, SM4, SM7), PCIe and other communication interfaces with advanced extensible interface-advanced high-performance bus three-level bus architecture. Findings This paper presents a high-speed cryptographic chip that integrates several high-speed parallel processing algorithm units. The test results of post-silicon sample shows that the high-speed cryptographic chip can achieve Gbps-level speed. That means only one single chip can fully meet the requirements of cryptographic operation performance for most cryptographic applications. Practical implications The typical application in this work is PCIe encryption card. Besides server’s applications, it can also be applied in terminal products such as high-definition video encryption, security gateway, secure routing, cloud terminal devices and industrial real-time monitoring system, which require high performance on data encryption. Social implications It can be well applied on many other fields such as power, banking, insurance, transportation and e-commerce. Originality/value Compared with the current strategy of high-speed encryption card, which mostly uses hardware field-programmable gate arrays or several low-speed algorithm chips through parallel processing in one printed circuit board, this work has provided a new PCIe encryption card solution with high performance, high integration and low cost only in one chip.

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